LCD Controller issues

[lpcware]

Content originally posted in LPCWare by bunrockter on Mon Sep 03 23:24:13 MST 2012
I am trying to get the LCD controller up and going on my LPC4350. I found a data sheet for the driver that is in the TFT display I am using (Newhaven) and I have set up the timing according to those values.

It is a 24 bpp model, but since the Hitex eval board doesn't have enough ram, I am running it in 16 bpp mode. I am sure the data lines don't match up, but I should still be able to get an image, the colors should just be off. Am I correct on that?

Anyways, I haven't been able to get an image on the LCD, so I decided to take a capture of the signals. My device doesn't have a very big buffer, so it is just the first line. However, I noticed that every time there is a pulse on the Hsync line that the enable line drops as well, is this the normal behavior?

I haven't had much experience with LPC MCUs, any help would be greatly appreciated. I will also attach the wave form. It is missing the clock, because it fills up the buffer pretty fast.


Thanks,

Bun

[lpcware]

Content originally posted in LPCWare by bunrockter on Thu Sep 27 14:09:10 MST 2012
Solved. I got the correct information from newhaven's engineering department, and things are up and running.

[lpcware]

Content originally posted in LPCWare by bunrockter on Mon Sep 03 23:42:47 MST 2012
Here are 2 more wave forms to show what happens on either side of a Vsync.

Also here is a listing of my configuration code if it helps:

LPC_RGU->RESET_CTRL0 = (1UL << 16);                           //Reset LCD
  waitUS(200);                                                //Wait 200 uS
 
  //while(LPC_RGU->RESET_CTRL0 &  (1UL << 16));               //Wait for reset bit to go low

  /* Clock polarity Reg */
  LPC_LCD->POL = (4UL << LCD_POL_PCD_LO_Pos) |                //Clock divider lower (LCDCLK/(PCDLO&PCDHI/2)) (20 MHz)
                  (0UL << LCD_POL_CLKSEL_Pos) |               //Clock source selection 0=internal 1= CLKIN
                  (0UL << LCD_POL_ACB_Pos) |
                  (0UL << LCD_POL_IVS_Pos) |                  //Invert VS
                  (0UL << LCD_POL_IHS_Pos) |                  //Invert HS
                  (0UL << LCD_POL_IPC_Pos) |                  //Invert Panel clock
                  (0UL << LCD_POL_IOE_Pos) |                  //Invert Data Enable (DE) Signal
                  ((800UL -1UL) << LCD_POL_CPL_Pos) |         //Clocks per line (25:16)
                  (0 << LCD_POL_BCD_Pos)|                     //TFT so bypass pixel clock (26)
                  (0 << LCD_POL_PCD_HI_Pos);                  //Clock divider upper

  /* Horizontal Timing Reg */
  LPC_LCD->TIMH = (((800UL/16UL)-1UL) << LCD_TIMH_PPL_Pos) |  //Pixels Per line value/16 -1 (7:2)
                  ((48U-1UL) << LCD_TIMH_HSW_Pos)|            //Horizontal Sync Pulse (15:8)
                  ((40UL-1) << LCD_TIMH_HFP_Pos) |            //Horizontal Front Porch (23:16)
                  ((88UL-1) << LCD_TIMH_HBP_Pos);             //Set Horizontal Back Porch (31:24)

  /* Vertical Timing Reg */ 
  LPC_LCD->TIMV = ((480UL - 1UL) << LCD_TIMV_LPP_Pos) |       //Lines per panel (9:0)
                  ((3UL-1UL) << LCD_TIMV_VSW_Pos) |           //Vertical Sync Pulse (15:10)
                  (13UL << LCD_TIMV_VFP_Pos) |                //Vertical Front Porch (23:16)
                  (32UL << LCD_TIMV_VBP_Pos);                 //Set vertical Back Porch 10 (31:24)
 
  /* Line End Control Reg */
  LPC_LCD->LE = 0;                                            //Not used for TFT display

  /* Upper Panel Frame Base Address Reg */
  //LPC_LCD->UPBASE = LCD_FRAME_BUFFER_0;                       //Set Upper frame buffer

  // LCD Control Register
  LPC_LCD->CTRL = (0UL << LCD_CTRL_LCDEN_Pos) |                 //LCD enabled (disable)
                  (4UL << LCD_CTRL_LCDBPP_Pos) |                //Bits per pixel  (4 = 16)
                  (0UL << LCD_CTRL_LCDBW_Pos) |                 //STN color / monochrome selection (not used for TFT
                  (1UL << LCD_CTRL_LCDTFT_Pos) |                //LCD panel type (TFT)
                  (0UL << LCD_CTRL_LCDMONO8_Pos) |              //Not used (STN) for TFT this must be set to 0
                  (0UL << LCD_CTRL_LCDDUAL_Pos) |               //Single or dual panel selection (single)
                  (0UL << LCD_CTRL_BGR_Pos) |                   //Color selection (RGB)
                  (0UL << LCD_CTRL_BEBO_Pos) |                  //Byte endianess (little)
                  (0UL << LCD_CTRL_BEPO_Pos) |                  //Pixel endianedd (little)
                  (0UL << LCD_CTRL_LCDPWR_Pos) |                //LCD Power enable (disabled)
                  (1UL << LCD_CTRL_LCDVCOMP_Pos) |              //Vertical compare interrupt (back porch)
                  (0UL << LCD_CTRL_WATERMARK_Pos);              //DMA to FIFO watermark level (replenish when 4 spots are free)

Later, the power is turned on, the frame buffer address is loaded, and the enable is set high.