Debugging Code in the QUIAD-SPI-FLASH memory

[lpcware]

Content originally posted in LPCWare by g.seidl on Mon Apr 07 01:32:31 MST 2014
Hello

we are using an NXP LPC1857 with internal Flash and an external QUADSPI Flash memory.The QUADSPI Flash is connected via the SPIFI interface. We are booting from the internal Flash but have some Code in the external QUADSPI Flash memory. Everything semms to work. But it is impossible to debug the code which is placed in the external QUADSPI Flash memory. When stepping into the code in the QUADSPI flash the debugger (j-link) terminates with the message "CPU is not halted Abort debug session?. We are using IAR Workbench 6.40 with j-link debugger. The question is now: Is it possible to debug code in the QUADSPI Flash via JTAG ?

[lpcware]

Content originally posted in LPCWare by TheFallGuy on Mon Apr 07 05:27:25 MST 2014
Take a look at the Cortex-M3 memory map:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0182h/CHDBFJED.html

Code must be located in the address range 0x0000 0000 thru 0x1fff ffff. This is because it is Harvard architecture.

This is probably why it is not debuggable in the 0x8000 0000 range.

[lpcware]

Content originally posted in LPCWare by g.seidl on Mon Apr 07 05:09:31 MST 2014
I have found the problem:
When looking at the LPC1857 memory map there are 2 areas
for the SPIFI Data:

1. 0x8000 0000 - 0x8800 0000 > 0x1FFFFFFF
2. 0x1400 0000 - 0x1800 0000 < 0x1FFFFFFF

When locating the code in the range 1: The code runs but no debugging possible.
When locating the code in the range 2: The code runs and debugging is possible.