DMA Response Time and GPIO

[lpcware]

Content originally posted in LPCWare by jcc273 on Tue Mar 19 07:26:43 MST 2013
This is on an LPC1788 running at 120MHz.

I setup a test for using DMA to write to GPIO.  Basically to support an old legacy communication platform i need to write 15 lines at a rate of ~8MHz.  I have my test working and i have everything being clocked at 120MHz.

The DMA is being triggered by a timer1 match.  I find that the absolute fastest the DMA can toggle the GPIO at is about 130nS.  The delay from when i see the external match line toggle to when i see the GPIO changed by the DMA is about 70nS.  Toggling the GPIO continuously in a while loop (LPC_GPIO2->SET=0x01;LPC_GPIO2->CLR=0x01) will toggle in 40nS.  So this would imply to me that the reaction time of the DMA to the signal from the timer 1 match is about 30nS(or the time it takes to read next value from RAM?). 

Does this delay seem legitimate to everyone?  i was thinking i would see a little faster of a response.  also i would have though writing GPIO from DMA might have been faster.

The additional 60nS to get to the 130nS max toggle rate seems to be the time i need to wait before signaling the next transfer or the dma misses it (time to get next value from RAM?).  It will not toggle any faster than 130ns.

At this point i am thinking of just moving to the LPC18xx series and running at 180MHz which should give me the extra little bit of speed i need.  However before i do so i am curious about AHB Matrix issues.  I can obviously keep my data to dma in a separate SRAM block on the matrix so there will be no contention there, but as for the GPIOs how are those treated?  are all the GPIO banks a single slave?  or is each bank (0,1,2,etc.) its own slave?  The data being dma'ed is time critical so i need to avoid contention.

My other option would be to dma to the 2 I2S ports on the LPC18xx running at 90MHz and pump the data out serially.  this is kind of what the current setup does in the legacy system; however, i would like to avoid this as this rate is waaaaay out of spec for the shift registers and counters.

Any thoughts or input is appreciated.  And the big question i need answered is how is GPIO treated on the AHB matrix, one slave or multiple?  THANKS : )

[lpcware]

Content originally posted in LPCWare by jcc273 on Mon Mar 25 12:53:00 MST 2013
You are my hero!  I didn't even think about using the LCD controller.  I wrote a quick test for this on friday using a 1788 eval board and it worked like a charm!  I set it up like it was controlling a TFT display in 5:6:5 mode and i was able write at a maximum rate of 40MHz, which is way more than my desired 8MHz rate.

Obviously i will have to work around the HSYNCs and VSYNCs but i think this method will definitely work for me.  I can set the bits per line to the lowest (16), set my VSYNC as small as possible (1 line), set my HSYNC to the min (13 DCLK Total), and set my number of lines rather high.  this will give me a sliding window to work with where i should be able to lay signal pairs within appropriate offsets to allow for exact communications.  As long as the number of clocks per line(16) is greater than the number of clocks in the HSYNC(13) then i should always be able to place the 2 pairs in spots along the window to get the exact amount of time desired between communication pairs : ).

Thank you very much for the suggestion!

[lpcware]

Content originally posted in LPCWare by wmues on Fri Mar 22 05:55:36 MST 2013
Have you checked if it is possible to use the LCD port for your data output?