4337 SSP0 not able to change clock frequency

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4337 SSP0 not able to change clock frequency

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by krhodesnb on Mon Feb 03 18:21:07 MST 2014
How do I change the clock frequency of an SSP channel, once it is running? This is required to support a SPI SSD interface. It needs to first be set to 400kHz, then change to 15MHz.

In the code snippet below, I show how I try to change the clock frequency, but when we look at it on a scope, it stays at 400kHz. We tried to not call IP_SSP_Set_Mode and IP_SSP_SetFormat, but no change.

Initialization:
#define SDC_SSI_DEVICE_BASE  LPC_SSP0
#define SSD_LOW_SPEED_CLOCK_FREQ    400000
#define SSD_HIGH_SPEED_CLOCK_FREQ    1500000

IP_SSP_Set_Mode(SDC_SSI_DEVICE_BASE, SSP_MODE_MASTER);
IP_SSP_SetFormat(SDC_SSI_DEVICE_BASE, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_MODE1);
Chip_SSP_SetBitRate(SDC_SSI_DEVICE_BASE, SSD_LOW_SPEED_CLOCK_FREQ);

Chip_Clock_Enable(CLK_MX_SSP0);
Chip_SSP_Enable(SDC_SSI_DEVICE_BASE);

Code to change the frequency:

Chip_SSP_Disable(SDC_SSI_DEVICE_BASE);
        Chip_Clock_Disable(CLK_MX_SSP0);
IP_SSP_Set_Mode(SDC_SSP_BASE, SSP_MODE_MASTER);
IP_SSP_SetFormat(SDC_SSP_BASE, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_MODE1);
Chip_SSP_SetBitRate(SDC_SSP_BASE, SSD_HIGH_SPEED_CLOCK_FREQ);
        Chip_Clock_Enable(CLK_MX_SSP0);
Chip_SSP_Enable(SDC_SSI_DEVICE_BASE);


Thanks.
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478 次查看
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by krhodesnb on Tue Feb 18 14:29:28 MST 2014
Just to close the ticket, removing the disable/enable calls works properly and I can dynamically change the clock frequency.

Thanks...Keith
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by krhodesnb on Wed Feb 05 12:44:13 MST 2014
Thanks.

So I can call Chip_SSP_SetBitRate alone and the clock should change as expected?

Thanks...Keith
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by wellsk on Tue Feb 04 09:30:31 MST 2014

Quote:
Chip_SSP_Disable(SDC_SSI_DEVICE_BASE);
Chip_Clock_Disable(CLK_MX_SSP0);
IP_SSP_Set_Mode(SDC_SSP_BASE, SSP_MODE_MASTER);



Clock enable and disable of the SSP is a possible problem here.
If you disable a peripheral clock, the peripheral may not work correctly. You'll likely lose the ability to program registers and may even get hard faults when you try to access the registers. Disabling the SSP clock via the Chip_Clock_Disable() function and then calling IP_SSP_Set_Mode(), etc. probably won't work.
Enable the SSP clock (once) before you use the SSP and then disable it after you are completely done with the SSP.
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