1778 NVIC - Undocumented IRQ

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Mon Sep 24 11:51:04 MST 2012
Investigation on a 1778 device (LQFP-208) has revealed that the NVIC implements 42 IRQs.

Only 41 are documented Watchdog to EEPROM.

Does anyone know what the extra one is for, and if it would be safe
to use it as a software triggered interrupt?

Cheers, Mike

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Tue Oct 02 08:18:56 MST 2012
Actually, SVC will not serve in my case; I am driving a custom display (not an LCD).

My display refresh runs 60*8 = 480 times a second.

This is high priority and only issues a strobe clock in hardware.

It also issues a software interrupt (quite low priority)
for a routine to load up the next raster row (1 of 8 rows)
if this is a multiple of 8 call, it also issues a software interrupt (low -- lower than the above -- priority) to generate the next frame buffer.

I was hoping to use (LPC1778) reserved Irq 13 and undocumented Irq 41.
Failing that, as I have no I2C, I would hijack two of these.

Other enabled interrupts are handling UARTS, Count down timers, Ethernet, Systick (up time counter) etc. etc.

[lpcware]

Content originally posted in LPCWare by Daniel Widyanto on Thu Sep 27 00:59:08 MST 2012
Hi Mike,

If you want to have software triggered interrupt, then it's the best to take advantage of SVCall exception. See the ARM Cortex-M3 Technical Reference Manual here (http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/DDI0337E_cortex_m3_r1p1_trm.pdf).

Your software based code will be portable to any ARM Cortex-M (including ARM Cortex-M0, M1, M3 and M4), and independent from any ARM vendor (NXP, STM32, AT91SAM, etc).

If you're looking for real implementation, check out the FreeRTOS project (http://www.freertos.org). The FreeRTOS is using SVCall to generate software based interrupt, to switch between the kernel and user mode.

Regards,
-daniel