ADC multi-channel sampling and DMA transfer in LPC55xx

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ADC multi-channel sampling and DMA transfer in LPC55xx

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ADC multi-channel sampling and DMA transfer in LPC55xx

The ADC converter for LPC55Sxx is a new IP, it has a lot of new features. The ADC converter clock frequency must be less than 24MHz, the ADC converter sampling rate can reach up to 1MSPS, the ADC converter supports to sample both the single-end analog signal and differential analog signal.

It supports software triggering mode and hardware triggering mode, the triggering source can be from internal Timer, external pins, comparator output signal. The ADC converter supports synchronous sampling for only single-ended analog channel, but the analog channel pair are fixed for example CH0A/CH0B and CH1A/CH1B.

The ADC of LPC55S6x consist of 16 Trigger Control (TCTRLa) registers, one trigger control register corresponds one hardware trigger source. For example, the TCTRL[0] corresponds trigger source0 GPIO irq_pint[0], the TCTRL[1] corresponds trigger source1 GPIO irq_pint[1].

When the GPIO IRQ_PIN[0] signal edge is detected, the ADC will be trigger to convert the analog channel.

Hardware trigger Mapped to

0 GPIO irq_pint[0]

1 GPIO irq_pint[1]

2 State Configurable Timer (SCT) sct0_outputs[4]

3 State Configurable Timer (SCT) sct0_outputs[5]

4 State Configurable Timer (SCT) sct0_outputs[9]

5 State Counter Timer (CTIMER) ct0_mat3_out

6 State Counter Timer (CTIMER) ct1_mat3_out

7 State Counter Timer (CTIMER) ct2_mat3_out

8 State Counter Timer (CTIMER) ct3_mat3_out

9 State Counter Timer (CTIMER) ct4_mat3_out

10 Comparator

11 ARM tx event

12 GPIO BMATCH

 

The trigger attributes is defined in the corresponding TCTRLaXX register, when the TCTRLaXX[HTEN]=0, software trigger is enabled, hardware trigger is disabled. Setting the SWTRIG[xx] bit will trigger ADC to start conversion.

The TCTRLaXX[TCMD] specifies which command buffer is executed.

 

There are 15 command buffers (CMDa), each consists of  two 32-bit registers

(CMDLa:CMDHa), which specifies the ADC channels, resolution, sampling time..

For all the examples, a hardware triggering mode example is developed, the hardware triggering source 7 “State Counter Timer (CTIMER) ct2_mat3_out” is used to trigger ADC, so TCTRL[7] register is initialized, the TCMD bits in TCTRL[7] register is set up as 1, so the CMDH[1]:CMDL[1] are initialized to configure the analog channel, ADC sample resolution… .

 

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‎07-08-2021 01:16 AM
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