FreeRTOSConfig.h in In the Kenetis SDK 2.0 examples

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FreeRTOSConfig.h in In the Kenetis SDK 2.0 examples

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davidfindlay
Contributor III

I hope this is the right place to post this. I am looking at the Kenetis SDK demo project for FreeRTOS using the SPI

 

FreeRTOSConfig.h includes these defines

 

/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5

 

Yet the code sets the interrupt priority to 2 for my processors SPI interrupt.

 

#if (__CORTEX_M >= 0x03)
#define SPI_NVIC_PRIO 6
#else
#define SPI_NVIC_PRIO 2
#endif

 

This seems to be incorrect according to everything I read. But I am hesitant to change my code from your example. Can you explain this?

 

Thanks

Labels (1)
3 Replies

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BlackNight
NXP Employee
NXP Employee

Hi David,

With setting the SPI interrupt to level 2 and configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY set to 5 means that the RTOS masks all interrupts up to level 5, and 2 is not masked. This means that the SPI interrupt shall *not* call any RTOS API calls as the RTOS does not map that interrupt. See as well ARM Cortex-M Interrupts and FreeRTOS: Part 3 | MCU on Eclipse for some details.

The above applies to Cortex-M3/M4/M7. For M0(+) configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY is not used as the hardware does not implement the BASEPRI register.

I hope this helps,

Erich

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davidfindlay
Contributor III

Okay. Makes sense now. We are using are core M0. Thanks.

0 Kudos

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danielchen
NXP TechSupport
NXP TechSupport

Hi David:

configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY is an interrupt boundary between two groups. One will get masked by RTOS critical secitons, and the other are never masked by RTOS critical sections and are therefore always enabled.  This applies to Cortex-M3, Cortex-m4, Cortex-M4F and Cortex-M7.

In addition, Kinetis K series supports 16 priority level for interrupts, Kinetis L series, only supports four priority levels for interrupts.

Regards

Daniel