Vhys

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davidsunsun
Contributor I

I am reading K24P144M120SF5. at section 2.2.1 table 1. 

VIH for 2.7V<Vdd<3.6V is 0.7*Vdd. 

ViL is 0.35Vdd. 

per my understanding of hysteresis, based on Vih and Vil, the Vhys should be 0.35*Vdd. 

could any one explain why Vhys specified in this table is 0.06*Vdd? 

Thanks,

David Sun

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egoodii
Senior Contributor III

Vih and Vil are the 'guaranteed' voltage points beyond which the logic-state of the pin can be assured to be properly interpreted.  Between Vih and Vil the evaluation of the input as a binary-state depends entirely on the exact 'doping' of the PMOS and NMOS transistors in the input stage.  Any one pin, on any of a range of devices, could expect to have a 'transition point' anywhere between those guaranteed Vih and Vil limits.

Vhys is entirely different.  It is a measure of the amount of 'positive feedback' around the input-stage that will help keep the 'current binary-state' a little beyond the aforementioned 'exact voltage' where any one particular input stage is balanced between '1' and '0' levels, as defined previously.  Vhys is there to guarantee that the input stage does not go 'truly linear' at that point, AND that the input can thus reject 'some' noise without creating a 'noisy' input state.

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davidsunsun
Contributor I

Thank you for your prompt response, and the detailed explaining, I think I have clear understanding of this levels now. 

David Sun

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egoodii
Senior Contributor III

Vih and Vil are the 'guaranteed' voltage points beyond which the logic-state of the pin can be assured to be properly interpreted.  Between Vih and Vil the evaluation of the input as a binary-state depends entirely on the exact 'doping' of the PMOS and NMOS transistors in the input stage.  Any one pin, on any of a range of devices, could expect to have a 'transition point' anywhere between those guaranteed Vih and Vil limits.

Vhys is entirely different.  It is a measure of the amount of 'positive feedback' around the input-stage that will help keep the 'current binary-state' a little beyond the aforementioned 'exact voltage' where any one particular input stage is balanced between '1' and '0' levels, as defined previously.  Vhys is there to guarantee that the input stage does not go 'truly linear' at that point, AND that the input can thus reject 'some' noise without creating a 'noisy' input state.

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