TWR_K65 SPI issue

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TWR_K65 SPI issue

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ameerhamza
Contributor III

Dear all,

I am using custom bare-metal application and trying to use TWR_K65 DSPI at maximum baud rate possible, the slave i am using supports upto 80 MHz clocking. I am running system clock at 180 MHz but due to some limitations, OUTDV_2 divider is set to 3 so bus clock is 60 MHz. And in SPI_CTAR0, both PBR (Baud Rate Prescaler) and BR (Baud Rate Scaler) are set to 0 (divided by 2) so we will have SPI Clock:

SPI_CLK = BUS_CLK / (PBR * BR) = 60 MHz ( 2 * 2) = 15 MHz.

Data gets corrupt i set above configuration. But if i set BR (Baud Rate Scaler) to 1 (divided by 3), I receive correct data, but it limits my clock to (10 MHz), I don't know why setting BR to 0 causing this problem, Any help would be highly appreciated.

Thanks,

Hamza.

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2 Replies

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jingpan
NXP TechSupport
NXP TechSupport

Hi Hamza,

Can you post your spi code here, include spi setting. For I'm not quit understand why you write out data 3 times in a loop, how you control the CS signal and how you finish a transfer.

Regards

Jing

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592 Views
jingpan
NXP TechSupport
NXP TechSupport

HI Ameer,

the max speed of K65 DSPI is 30M in master mode(in slave mode only 10M). Since you use TWR-K65 board, the voltage supply also should be ok. So I guess the problem may in timing issue. You may try to adjust the timing issue or observe the waveform by oscilloscope. If the problem is still there, you can share your code and the wifi module's spec here. I'll try to debug for you.

Regards

Jing