mjbcswitzerland wrote:
If you have a 24MHz crystal instead of 16MHz and you also use this as PLL reference there are two (or three) adjustments to make:
1. For the HS transceiver's PLL you need to set USBPHY_PLL_SIC to the 24MHz divide.
2. You need to ensure that the clock input divider is set to 2 or 3 so that the MCG's PLL's is between 8MHz and 16MHz (unless already matching)
3. You need to ensure that the PLL settings are correct for the PLL to be able to lock (eg. x20 for 120MHz from 12MHz)
Thanks again Mark! This is helping me understand of how the SoC clocks are configured. I found that the K65 startup code I'm porting from had the following defined in src / include / device / MK26F18 / system_MK26F18.h :
#define CLOCK_SETUP 4
This is then used in src / startup / MK26F18 / system_MK26F18.c to configure the clocks for USB operation.
Now, the target enters a signal handler when it executes the following:
#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
#endif
I can get passed this call if I single-step through SystemInit() but it will enter the signal handler on the next clock configuration immediately following the code above:
#if defined(SYSTEM_SIM_CLKDIV3_VALUE)
SIM->CLKDIV3 = ((SIM->CLKDIV3) & (uint32_t)(~(SIM_CLKDIV3_PLLFLLFRAC_MASK | SIM_CLKDIV3_PLLFLLDIV_MASK))) | ((SYSTEM_SIM_CLKDIV3_VALUE) & (SIM_CLKDIV3_PLLFLLFRAC_MASK | SIM_CLKDIV3_PLLFLLDIV_MASK)); /* Selects the PLLFLL clock divider. */
#endif
I'll stare at this some more and refer to the reference manual to see if I can figure out how this could fail.
What is your budget for the port (in man-hours or dollars)?
Or are you doing it for hobby/fun?
I use a K26 at work but this bootloader development is just fun/learning.