Sequential sampling, COCO and lock mecanism of PDB

[simongodfrind]

Dear all,

Considering I have read posts about the question without finding the answer I formulate it here.

Checking the AN5380 "Using FTM, PDB, and ADC on KE1xF to Drive Dual PMSM FOC and PFC"

And reading the behaviour of PDB with the lock mecanism in the "Kinetis KE1xF Sub-Family Reference
Manual" that says: "When a pre-trigger from a PDB channel n is asserted, the associated lock of the pre-
trigger becomes active. The associated lock is released by the rising edge of the
corresponding ADCnSC1[COCO]; the ADCnSC1[COCO] should be cleared after the
conversion result is read, so that the next rising edge of ADCnSC1[COCO] can be
generated to clear the lock later. "

1) I wonder first if there is a way to not being blocked by COCO vs PDB lock to sequentially sample mutliple input then issue an ISR and then reading all the Results at once without the use of DMA (that clears COCO), Average function or Compare function (that prevent COCO from being set).

2) Secondly if it is not possible only, how in AN5380 do they achieve to sample the offset of the Fan Motor at 10kHz? Because in Fig. 5 (copied below), I don't see any ISR that would read specifically the result of it to clear COCO (and unblock PDB CH0DLY1) whereas the ADC continue to sample both PFC currents just after (same question btw between both PFC current sampling) ? I am obviously missing something.

3) Only if not answered regarding the 2 questions before, what would be the best solution to sample 2 signals simultaneously then, after the conversion time, 2 others simultaneously then, after the conversion time, process them into a single ISR? In fact, I'd like to minimise any unnecessary ISR's to release the PDB channel pretrigger lock.

PS: Of course, the access to the whole source code of this application note would make it easier. 

Thanks in advance,

[xiangjun_rong]

Hi, Simon,

As you know that KE1xF has three ADC converter:ADC0,ADC1,ADC2, each ADC has 8 register group, for example for ADC0, this is the ADC0 Register group:  ADC0_SC1A/ADC0_RA, ADC0_SC1B/ADC0_RB, ADC0_SC1C/ADC0_RC, ADC0_SC1D/ADC0_RD, ADC0_SC1E/ADC0_RE, ADC0_SC1F/ADC0_RF, ADC0_SC1G/ADC0_RG, ADC0_SC1H/ADC0_RH. Ecah ADC0_SC1y has it's corresponding COCO bit, in other words, there are 8 COCO bits from ADC0_SC1A to ADC0_SC1G. The PDB has to generate 8 triggering pulse to trigger ADC to sample 8 ADC channel sequentially from ADC0_SC1A, ADC0_SC1B.....ADC0_SC1G, during the time from the ADC triggering signal start to the corresponding COCO signal rising edge, the ADC converter is locked lest the ADC convertion is interrupted by another triggering signal, when the corresponding COCO bit is set, the ADC lock is released so that ADC can accept aother ADC triggering signal.

Q1) I wonder first if there is a way to not being blocked by COCO vs PDB lock to sequentially sample mutliple input then issue an ISR and then reading all the Results at once without the use of DMA (that clears COCO), Average function or Compare function (that prevent COCO from being set).

>>>>>>>>>>>>As I said above, the ADC is blocked by COCO bit or signal during the ADC conversion, there is not any awy to unblock ADC during ADC conversion.

Q2) Secondly if it is not possible only, how in AN5380 do they achieve to sample the offset of the Fan Motor at 10kHz? Because in Fig. 5 (copied below), I don't see any ISR that would read specifically the result of it to clear COCO (and unblock PDB CH0DLY1) whereas the ADC continue to sample both PFC currents just after (same question btw between both PFC current sampling) ? I am obviously missing something.

>>>>>>>>>>>>In the AN5380, the PDB is synchronized by FTM0, which is 5KHz, so the PDB is also 5KHz, if you sample the same ADC channel twice in the PDB one period, the sampling frequency is 10KHz. The PDB can generate 8 triggering signals to sample analog channel, so you can set for example the ADC0_SC1A and ADC0_SC1F to the same ADC analog channel, the analog channel will be sampled twice in one PDB period.

Q3) Only if not answered regarding the 2 questions before, what would be the best solution to sample 2 signals simultaneously then, after the conversion time, 2 others simultaneously then, after the conversion time, process them into a single ISR? In fact, I'd like to minimise any unnecessary ISR's to release the PDB channel pretrigger lock.

>>>>>>>>>>>>in the AN5380, the FTM0/FTM3 are synchronized, PDB0 and PDB1 are synchronized with FTM0, so PDB0 and PDB1 are synchronized, you can set the PDB0_CH0_DLY0 and PDB1_CH0_DLY0 the same value, the analog channel in ADC0_SC1A and ADC1_SC1A will be sampled simultaneouslly.

Hope it can help you

BR

Xiangjun Rong