Replace KL27 with K32L2A

[jh0]

Hi,

I want to upgrade KL27 based project with new K32L2A (same 64 LQFP package and pinout), to have higher speed and more Flex IO shift / timer.

KL27 is working on 48 MHz CPU clock with 24 MHz flash clock. Each assembler register operation executing from flash will take one CPU cycle. Port access that is in CPU domain (IOPORT) will take one CPU cycle.

I want to know what will be situation with K32L2A with HSRUN 96 MHz CPU clock (and 24 MHz flash clock). Assembler register operation executed from flash will take one CPU cycle? IOPORT access will take one CPU cycle? What is downside of running in HSRUN mode except higher current consumption?

Thank you,

Josip

[jingpan]

Hi,

1.Do you mean read/write a register from flash controller or FTFA? That is via bus interface clock. Please look at table 5-1 in reference manual. Reading FMC register base on DIVCORE_CLOCK. Reading FTFA base on DIVSLOW_CLK.

2. One of the GPIO module feature is zero wait state access to GPIO registers through IOPORT. The GPIO module is clocked by system clock. It is same with core clock.

3. When the MCU is in HSRUN mode, the user has no access to the flash command set when the MCU is in
HSRUN mode.

Regards

Jing

[jh0]

I am thinking on executing program from flash memory. For example this assembler instruction...

ADCS R3, R3

on KL27 at 48 MHz core clock and 24 MHz flash clock will be executed in one CPU cycle. My question is if it will be executed on K32L2A at 96 MHz core clock and 24 MHz flash clock, in one CPU cycle? Same question for...

STRH R4, [R5]

where R5 is from IOPORT domain. It will be executed in one CPU cycle on KL27 at 48 MHz core clock and 24 MHz flash clock. Repeat, in both cases program (assembler instruction) executing from flash memory.

I don't use flash (controller) command set, so (for me) this HSRUN mode limitation is irrelevant.

Regards,

Josip

[jingpan · Accepted solution]

Hi,

If the instruction has been load into flash cache, of course it will be fetched and executed. But in some case, like right after a jump instruction and it is not in flash cache, MCU has to wait. But at least, it won't worse than KL27. There bus and flash structure are same.

K32L2A Flash has 64-bit wide banks. That means each time it can read out 4 instruction. It has a 64-bit speculation buffer can prefetch the next 64-bit flash memory location. If the instruction execute in order, there wont be any delay.

Regards,

Jing