Processor Expert ADC_LDD pin initialization problem

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Processor Expert ADC_LDD pin initialization problem

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johns_chuang
Contributor III

Dear Team,

I've configured PTA1, PTB2, and PTB3 pins as ADC inputs using ADC_LDD, and the ADC functionality works as expected. However, the other three GPIOs configured as outputs in the PTCx group are being affected. Upon startup, these GPIOs are initially set to a high state before returning to the low state.

The ADC code are attached below. When I disable the two commands shown in the image, the PTCx group in the GPIOs behave normally.
ADC_Init.JPG

 

GPIOs output after enabling ADC readings:

LeCroy3.jpg

 

When the ADC is closed:

ADC_unInit.JPG

What GPIO should look like:

LeCroy5.jpg

 

Could you please advise on how to identify and resolve the issue in the code? Or is it a hardware limitation preventing this pin definition? Are there any methods to use ADC_LDD without impacting the initial values of PTCx group in the GPIOs?

 

Regards,

Johns

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

As the following figure I copied from the KEA8RM.pdf,  the PTC1, PTC3 pins function as ADC analog input channel with on-chip pull-up disabled, PTC5 pin is default state or in float mode with on-chip pull-up disabled.

After Reset, because you do not connect external pull-up or down resistor, and all the pins are in input or float state, when you connect a scope, the pin voltage is subject to external noise, it may be in low, high or middle voltage. After you configure the pin in GPIO mode, because the pin is also in input mode, the pin voltage is subject to external noise. After you configure the pin in GPIO mode and output mode, the pin will be driven to be high or low logic, the pin will be low or high, is not subject to noise. When you configure the pin in GPIO mode and output High logic, the pin voltage will be equal to VDD, the VDD voltage can be 5V.

If you want to get fixed voltage on the PTC1/C3/C5, pls connect external pull-up or down resistor.

Hope it can help you

BR

XiangJun Rong

 

 

 

xiangjun_rong_0-1702894884953.png

 

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johns_chuang
Contributor III

Hi XiangJun,
I apologize for the imprecise illustration. In the original diagram, the yellow represents MCU's VDD, the red depicts the 1.1V voltage sequence triggered by PTC3, the green shows the 1.8V voltage sequence triggered by PTC1, and the blue displays the 3.3V voltage sequence triggered by PTC5. Hence, the varying high and low voltages don't indicate the actual GPIO output levels, but they still reflect the high and low states of the GPIO output.

However, if you look at the GPIO alone, it appears as in the following diagram (using PTC1 as an example).

johns_chuang_0-1702260761338.png

 

I am using the built-in BitsIO_LDD functionality, configured as shown in the image below. We set the relevant IOs as outputs and default them to a low level.

johns_chuang_1-1702260795859.png

 

I've also tried adding the following code, but it hasn't improved the situation.

GPIOA_PCOR |= GPIO_PCOR_PTCO(0x003FE000);

 

Is there anything else we can check? 

 

Thank you for your assistance.

 

Regards,

Johns

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

Can you tell us the part number of Kinetis family?

From your description "the red depicts the 1.1V voltage sequence triggered by PTC3, the green shows the 1.8V voltage sequence triggered by PTC1, and the blue displays the 3.3V voltage sequence triggered by PTC5", do you mean that the PTC3, PTC1 and PTC5 are multiplexed with ADC analog channels?

BR

XiangJun Rong

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johns_chuang
Contributor III

Hi XiangJun,

Thank you very much for your response. I'm using the s9keazn8.

In the picture, the yellow is the MCU's VDD, and the other three colors are the output GPIOs of PTC1, PTC3, and PTC5. My ADC is using PTA1, PTB2, and PTB3.

Does this mean it's ADC multiplexing as you mentioned?

Regards,

Johns

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

As the following figure I copied from the KEA8RM.pdf,  the PTC1, PTC3 pins function as ADC analog input channel with on-chip pull-up disabled, PTC5 pin is default state or in float mode with on-chip pull-up disabled.

After Reset, because you do not connect external pull-up or down resistor, and all the pins are in input or float state, when you connect a scope, the pin voltage is subject to external noise, it may be in low, high or middle voltage. After you configure the pin in GPIO mode, because the pin is also in input mode, the pin voltage is subject to external noise. After you configure the pin in GPIO mode and output mode, the pin will be driven to be high or low logic, the pin will be low or high, is not subject to noise. When you configure the pin in GPIO mode and output High logic, the pin voltage will be equal to VDD, the VDD voltage can be 5V.

If you want to get fixed voltage on the PTC1/C3/C5, pls connect external pull-up or down resistor.

Hope it can help you

BR

XiangJun Rong

 

 

 

xiangjun_rong_0-1702894884953.png

 

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johns_chuang
Contributor III

Hi XiangJun,

Thank you for your detailed explanation. Indeed, TC1, TC3, and TC5 have external pull-down resistors. However, my primary confusion lies in the fact that, when using AD1_GetMeasuredValues() during each startup, TC1, TC3, and TC5 exhibit high voltage. Strangely, when I mask AD1_GetMeasuredValues(), TC1, TC3, and TC5 display normal readings. Do you have any insights into this?

johns_chuang_0-1702947901532.png

 

PS. If the abnormal high voltage is disregarded, both GPIO and ADC functions operate normally.

Regards,

Johns

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xiangjun_rong
NXP TechSupport
NXP TechSupport
Hi,
I suppose that you sample the PTC1/PTC3 analog channels, as you know that there is a Sample/Hold capacitor for the ADC converter, when the ADC samples the analog channels, the pin will become low impedance, it takes effect the channel if you connect a scope to the analog channels.
If you do not sample the channels with AD1_GetMeasuredValues() , but the analog channels are effected, I am sorry, I can not explain.
BTW, I suggest you connect 5K~10K ohm external resistor.
Hope it can help you
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johns_chuang
Contributor III
Hi XiangJun,

I've revamped the program framework and traced the issue to one of my subroutines. Thanks for your help and guidance.

Regards.
Johns
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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

For multiplexed pins, as you know that you assign a pin a specific function with configuring the PORTx_PCRy register. When you set the MUX bits as 0, it is analog function, when you set the MUX bits as 1, the pin will function as GPIO. Because of default pull up or down resistor enabled in the PORTx_PCRy register, the pin may see as high logic or low logic when the pin is float.

So for the first GPIO figure, the I/O voltage jump in different level, this is my analysis.

1)Enabling PORTx gated clock by writing  corresponding bit in SIM_SCGCx reg.

2)for example,write the PORTx_PCRy register with MUX bits 1, you configure the GPIO pin in GPIO input mode, the case, the GPIO will be in INPUT mode, the default pull-up resistor will pull the GPIO pin logic to a middle level.

3)you write the GPIO direction register as output and output High logic, the GPIO pin voltage will jump to VDD.

In conclusion, pls check your code to configure the PORTx_PCRy and GPIO direction reg and GPIO output reg.

Hope it can help you

BR

XiangJun Rong