For a product that does not require low power modes and does not operate on batteries.
If the reset pin is disabled future SWD programming is possible ?
In a product where the reset pin is not used, this pin should be left as reset or set as GPIO ?
If left as reset function, it should have additional 100nF capacitor added to it and additional external pull-up like 10K or 4K7 resistor ?
MKW40Z/30Z/20Z Reference Manual, Rev. 1.2, 10/2015
6.2.2.1 External pin reset (RESET_b)
This pin is open drain and has an internal pullup device. Asserting RESET_b wakes the device from any mode.
The RESET_b pin can be disabled by programming RESET_PIN_CFG option bit to 0.
When this option is selected, there could be a short period of contention during a POR ramp where the device drives the pin-out low prior to establishing the setting of this option and releasing the reset function on the pin. When the RESET pin is disabled and configured as a GPIO output, it operates as a pseudo open drain output.
6.2.2.9 MDM-AP system reset request
Set the System Reset Request field in the MDM-AP control register to initiate a system reset. This is the primary method for resets via the SWD interface. The system reset is held until this field is cleared. Set the Core Hold Reset field in the MDM-AP control register to hold the core in reset as the rest of the chip comes out of system reset.
6.2.4 RESET_b pin
For all reset sources except a VLLS Wakeup that does not occur via the RESET_b pin, the RESET_b pin is driven low by the MCU for at least 128 bus clock cycles and until flash initialization has completed.
After flash initialization has completed, the RESET_b pin is released, and the internal Chip Reset negates after the RESET_b pin is pulled high. Keeping the RESET_b pin asserted externally delays the negation of the internal Chip Reset.
The RESET_b pin can be disabled by programming FTFA_FOPT[RESET_PIN_CFG] option bit to 0 (See Table 6-2). When this option is selected, there could be a short period of contention during a POR ramp where the device drives the pin low prior to establishing the setting of this option and releasing the reset function on the pin. When the RESET pin is disabled and configured as a GPIO output, it operates as a pseudo open
drain output.
Table 6-2. Flash Option Register (FTFA_FOPT) bit definitions
RESET_PIN_CFG Enables/disables control for the RESET pin.
0 RESET pin is disabled following a POR and cannot be enabled as reset function.
When this option is selected, there could be a short period of contention during a
POR ramp where the device drives the pinout low prior to establishing the setting
of this option and releasing the reset function on the pin.
This bit is preserved through system resets and low-power modes. When RESET
pin function is disabled, it cannot be used as a source for low-power mode wakeup.
NOTE: When the reset pin has been disabled and security has been enabled by
means of the FSEC register, a mass erase can be performed only by
setting both the Mass Erase and System Reset Request fields in the
MDM-AP register.
