MK70FN1M0VMJ12 UART FIFO implementation

[praveenkumari]

Hello team,

We are working on MK70FN1M0VMJ12 micro controller and need to implement FIFO in UART0 and UART1.

Can you please clarify the following information:

1) How to read Receive Buffer data when FIFO is enabled in UART module and watermark level is set?

2) Do you have any sample code or document explaining UART FIFO usage?

[isaacavila]

Hello,

For Rx FIFO implementation, you can read data from UARTx_D register as it is made in normal implementation (no FIFO feature enabled). Difference between no FIFO and FIFO implementation is the times you need to read UARTx_D register and when RDRF is set. For example, imagine that you set Rx FIFO's watermark to 6 (Remember that both UART0 and UART1 have 8-datawords FIFOs), RDRF flag will be set onlye when 6 or more data are received, once these 6 (or more) bytes are received, RDRF will be set and you will need to get these data from UARTx_D register "UARTx_RCFIFO" times.

Attached you can find a basic example for Rx FIFO implementation, basically, it enables UART0's Rx FIFO feature, sets watermark to FIFO_SIZE/2 (4) and enables Receiver's interrupt. When 4 or more bytes are received, these data is taken from Rx FIFO and they are stored in internal buffer, then, they will be sent back to terminal. It is a bareboard project created for FRDM-K64F board (in KDS), however, same principle applies for K70's MCU.

Hope this helps!

Regards,

Isaac

[praveenkumari]

Hello Isaac,

Thanks for your reply.

Could you clarify the maximum size of UART0 and UART1 Transmit, Receive FIFO size in bytes for

MK70FN1M0VMJ12.

Because you said it is having 8-datawords, in Reference Manual UART configuration information says 8 entries, in UART0_PFIFO register says configurable up to 128-datawords.

What entry means? Databyte or Dataword?

This confusion arises because in UART configuration information,

UART0 and UART1 contains 8-entry transmit and 8-entry receive FIFOs

All other UARTs contain a 1-entry transmit and receive FIFOs

All other UARTs are only able to receive 1 Byte. Is that right?

Regards,

Praveenkumar I

[egoodii]

"...UART0_PFIFO register says configurable up to 128-datawords."

Like all other elements of Kinetis reference manuals, the peripheral description outlines the 'maximum potential design capacity'.  Chapter 3 of each manual defines the characteristics selected to instantiate that peripheral within any particular silicon, and for this part UART0/1 have 8 bytes/entries, the others 1 (simple double-buffered function).

The 'dataword' terminology for the FIFO comes about because the 'FIFO logic' includes not ONLY the '8 bits of UARTx_D', but also other associated bits, including the potential ninth bit (R8, read in register C3) and NOISY and PARITYE status bits (UARTx_ED) to go with the databyte.

One other design-note:  If you are going to use these expanded FIFOs and watermark-interrupts, I suggest you will also want to enable an 'idle line interrupt' to prompt your routine to empty the 'last few' (less than watermark, no more coming) from the FIFO.

[isaacavila]

Hello,

Every entry is a 8-bit location (indeed it is the size for UARTx_D register), so, for UART0 and UART1, you have 8 bytes in the FIFO and all other UART are 1-byte entry.

Hope this helps!

regards,

Isaac