Hi everyone!
I am using a NXP K66 board (FRDM-K66F with MK66FN2M0 to be precise) and
I am trying to achieve the maximum possible conversion rate with the on chip ADCs.
According to the technical datasheet, Table 31 in 3.6.1.1, the ADC clock can be between 1 and 24 MHz, regardless the source. According to the reference manual, 39.5.1, the clock source for the ADC clock be one of
- Bus clock (60 MHz in my case)
- Bus clock divided by two (30 MHz in my case)
- Alternate clock (12 MHz on the FRDM-K66F, as it is derived from an external crystal which happens to be 12 MHz)
- Asynchronous clock (9.5 MHz at absolute maximum, according to the technical datasheet, Table 32 in 3.6.1.2)
In order to use a faster clock than alternate or asynchronous clock, Bus clock has to be used, which needs to be divided using CFG1[ADIV], so that it falls within the legal range of ADC clock. As the possible divider values are only 1, 2, 4 and 8, as described in the reference manual 39.4.2, this means that the maximum ADC clock value is 15 MHz (using divide-by-4, as using divide-by-2 results in 30 MHz, which is too fast for the ADC).
Do I miss something? Is there a possibility to derive a faster Bus clock to boost the ADC clock?
E.g., if the Bus clock was 90 MHz, one could get 22.5 MHz, getting close to the maximum 24 MHz for the ADC clock.
Does anyone have a suggestion on how to achieve this? Is it possible? Is there another option to achieve a higher ADC clock than 15 MHz?
Thanks!
