Loss of Clock reset when waking from stop mode

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Loss of Clock reset when waking from stop mode

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dereksnell
NXP Employee
NXP Employee

I wanted to point this out after working on an issue.  The snippet from the reference manual below shows the MCG clock monitor needs to be disabled when entering any stop mode, VLPR, or VLPW.  This is done by clearing the CME bit in MCG_C6.  If CME is set when entering a low power mode, it can cause resets.  As of MQX v3.8.1, some BSPs do have the CME bit set when entering a low power mode.  This issue has already been reported to the MQX team.

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