LPSPI on FRDMKEA16Z works only for a few seconds

[attiliorossi321]

Hi guy.

I'm new about the LPSPI driver.

I'm using a freedom board based up on KEA16Z. I find this kind of SPI port rather difficult. I got some example code  to understand this driver, but it'doesn't work jet properly.

I post this code hoping someone can explain why it doesn't work. 

The problem is that I can see the tx output data on mosi and the signal clock too on SCKpin

But this happen only for for 8 times.

Infact I call the function every 2 second, and I'd like to see the impulse train just forever every 2 second.

But after 8 transmission the clock pin goes high and  the sistem is locked, of course.

Here is the init code, below the call.

void LSPI_Init(void)

{

          PCC->CLKCFG[PCC_LPSPI0_INDEX] |= PCC_CLKCFG_CGC_MASK;                                    //            PCC->CLKCFG[PCC_PORTE_INDEX]  |= PCC_CLKCFG_CGC_MASK;                                                 PORTE->PCR[0] = PORT_PCR_MUX(2);                                                                                   // 

         PORTE->PCR[1] = PORT_PCR_MUX(2);                                                                                   // 

         PORTE->PCR[2] = PORT_PCR_MUX(2);                                                                                   //

         LPSPI0->CR    = 0x00000000; /* Disable module for configuration */

         LPSPI0->IER   = 0x00000000; /* Interrupts not used */

         LPSPI0->DER   = 0x00000000; /* DMA not used */

         LPSPI0->CFGR0 = 0x00000000; /* Defaults: */

                                /* RDM0=0: rec'd data to FIFO as normal */

                                /* CIRFIFO=0; Circular FIFO is disabled */

                                /* HRSEL, HRPOL, HREN=0: Host request disabled */

         LPSPI0->CFGR1 = 0x00000001; /* Configurations: master mode*/

                                /* PCSCFG=0: PCS[3:2] are enabled */

                                /* OUTCFG=0: Output data retains last value when CS negated */

                                /* PINCFG=0: SIN is input, SOUT is output */

                                /* MATCFG=0: Match disabled */

                                /* PCSPOL=0: PCS is active low */

                                /* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full */

                                /* AUTOPCS=0: does not apply for master mode */

                                /* SAMPLE=0: input data sampled on SCK edge */

                                /* MASTER=1: Master mode */

         LPSPI0->TCR   = 0x53000008; /* Transmit cmd: PCS3, 16 bits, prescale func'l clk by 4, etc*/

                                /* CPOL=0: SCK inactive state is low */

                                /* CPHA=1: Change data on SCK lead'g, capture on trail'g edge*/

                                /* PRESCALE=2: Functional clock divided by 2  */

                                /* PCS=3: Transfer using PCS3 */

                                /* LSBF=0: Data is transfered MSB first */

                                /* BYSW=0: Byte swap disabled */

                                /* CONT, CONTC=0: Continuous transfer disabled */

                                /* RXMSK=0: Normal transfer: rx data stored in rx FIFO */

                                /* TXMSK=0: Normal transfer: data loaded from tx FIFO */

                                /* WIDTH=0: Single bit transfer */

                                /* FRAMESZ=15: # bits in frame = 15+1=16 */

         LPSPI0->CCR   = 0x0409080A; /* Clock dividers based on prescaled func'l clk of 100 nsec */

                                /* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */

                                /* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) */

                                /* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */

                                /* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) */

         LPSPI0->FCR   = 0x00000001; /* RXWATER=0: Rx flags set when Rx FIFO >0 */

                                /* TXWATER=3: Tx flags set when Tx FIFO <= 3 */

         LPSPI0->CR    = 0x00000009; /* Enable module for operation */

                                /* DBGEN=1: module enabled in debug mode */

                                /* DOZEN=0: module enabled in Doze mode */

                                /* RST=0: Master logic not reset */

                                /* MEN=1: Module is enabled */

}

This every two seconds.

void TestSpi(void)

{

  while((LPSPI0->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0); 

  LPSPI0->TDR = 0x12;                                                

  LPSPI0->SR |= LPSPI_SR_TDF_MASK;                

}

Thanks in advance.

Attilio

[diego_charles · Accepted solution]

Hi Attillo,

I have noticed that you are creating a master with using  a polling method  and   the FRDM-KE16Z, is this correct?

Being that the case, I believe that taking a look at our SDK LPSPI demos will be  worthwhile as a reference. For  example lpspi_polling_b2b_transfer.

If you have any issues to download an SDK example, you may check this tutorial

MCU Tech Minutes | Importing an SDK Package into MCUXpresso IDE

This week we had an intense workload, and my reply had been delayed, my apologies!

Please let me know If I can help you further,

BR , Diego

[attiliorossi321]

Hi Diego.

You are right. I have just seen the correct example about lpspi. It does a lot of things.

Don't be worry about your answer. It's just in time.

Many thanks.

Attilio