KL26Z UART with DMA Tx fails with baud > 115200

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KL26Z UART with DMA Tx fails with baud > 115200

Contributor I

I have been looking into a problem with using DMA transfers with the UART on a FRDM-KL26Z development board.  I have replicated the problem using one of the driver sample codes for the Kinetis SDK v2.

The example code is located in the following directory of the KSDK v2 folder:


This code builds and runs just fine with the default baud rate of 115,200 bps.  However changing the baud rate to the next highest standard value of 230,400 bps results in a hard fault when attempting to enable the UART Tx DMA.  I have traced the hard fault back to where a KSDK library function (UART_EnableTxDMA() in fsl_uart.h) attempts to set the Transmitter DMA Select bit "TDMAS" in the UART1_C4 register.

Is this expected behaviour ?  My reading of the KL26Z reference manual and other information suggests UART DMA transfers should be capable of much higher speeds.

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2 Replies

NXP Employee
NXP Employee

Hi Geoff

Problem here is that UART1 not DMA transfer. In KL26Z UART1 and UART2 modules operate from the bus clock. When you run BOARD_BootClockRUN of the example, you set Core clock: 48MHz and Bus clock: 24MHz. Then, when you UART_Init there is a part where it calculates the baud rate modulo divisor and after this you can find:

/* next, check to see if actual baud rate is within 3% of desired baud rate
     * based on the calculate SBR value */
    if (baudDiff > ((config->baudRate_Bps / 100) * 3))
        /* Unacceptable baud rate difference of more than 3%*/
        return kStatus_UART_BaudrateNotSupport;

When you try to set 230400 you don't have the 3% desired baud rare difference, and you fall here, returning a error status (that is never checked in the main file) and it didn't set the UART module. So when you try to call enable Tx transfers it fall in the hard fault.

Best Regards

Jorge Alcala

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Specialist V


I know of no problems with the UART/DMA in the KL26.

Attached is a binary which you can load to the FRDM-KL26Z which will send a few hundred characters at 3MBaud out of the UART 0 every 50ms (visible also on J1-4 since it is too fast for the OpenSDA).

At the same time - it operates as USB-CDC (when connected by the KL26 USB connector) to show that both are possible in parallel (remembering that UART DMA and USB are both contending for the bus).

Below is the simulation where I also didn't see how DMA should be ale to fail:




Kinetis for professionals: http://www.utasker.com/

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