Hi Lance,
Sorry for the later reply.
The frame sync clock will based on SAI Transmit Configuration 4 Register (I2Sx_TCR4) [SYWD] bit about active level bit clock number. When, set data frame with 2 words, each word 32 bit, the total frame sync signal bit clock is (32bit active level + 32bit inactive level, total 64bit ).
When customer need just three clock signals output, it need to continue to transmit the data output(whatever the data value). So, there need to use DMA engineer to move data to SAI Transmit Data Register (I2Sx_TDRn) continuously.
We are curious why customer consider this kind of application of SAI module.
We also suggest customer to use PTC3(CLKOUT) pin to output the I2S_MCLK clock(OSCERCLK) ;
using two TPM modules to output SAI_TX_BCLK clock and SAI_TX_FS clock.
Wish it helps.
Have a great day,
Ma Hui
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