K70 Tower System MQX Application in RAM

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K70 Tower System MQX Application in RAM

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twadepgh
Contributor I

I'd like to find an example MQX application that executes from the K70 Tower System DDR memory.  So far, I haven't found any examples that seem to apply and the ones I've seen that locate things in external memory seem to be incomplete.  I've made changes to my linker configuration that look to me like they should work, but when I load the app to the target, the code runs into the weeds.  Realizing that MQX attempts to initialize DDR, I am aware that I may need to skip some of those steps.

BTW: I have a startup TCL script that configures DDR so my app can be loaded to it.  It's the "init_twr_ddr2.tcl" script that Freescale provides for bringing the K70 up with DDR configured.

Thanks in advance,

Todd

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Carlos_Musich
NXP Employee
NXP Employee

Hi Todd,

The task you want to perform is not easy with MQX. You can find below the steps I followed do it.

1.- Create a new MQX3.8.1 project in CW10.2 using the New Project wizard and select it in the CodeWarrior projects workbench. I will call this project 'K70_MQX_DDR2_Target'.

NOTE: Make sure that your connection type is OSBDM. This project is not tested with J-link.

2.- Click menu Project > build Configurations > Manage

3.- Click New. In the window prompted name your new Build Configuration K70_EXT_DDR2 and select Copy Sttings from Existing Configuration. Select Internal RAM, click OK and click OK again.

NOTE: Make sure that the active Build Configuration is the one that was just created. Check this in menu > Project > Build Configurations > Set active

4.- Create 'Linker_Files' folder inside Projects_Settings Folder and copy K70_DDR2.lcf contained in this attachment.

5.- Click menu Project > Properties > C/C++ Build > Settings > ColdFire Linker > Input and browse for K70_DDR2.lcf. Click OK.

NOTE: Some edits must be done to the BSP. The reason is that the clock and the DDR2 module are configured by the debugger using init_twr_k70_ddr2.tcl. But MQX has its own clock and DDR2 configuration. If MQX overwrites these configurations the debug session will fail. So we need to avoid that MQX initializes the PLL and the DDR2.

6.- Go to line 995 in bsp_cm.c. This file is located in C:\Freescale\Freescale MQX 3.8\mqx\source\bsp\twrk70f120m. Below you can find the code snippet that must be disabled. To disable the code I put it between #if 0... #endif directives.

#if 0

/* MCG_C7: OSCSEL=0 */

  MCG_C7 &= (uint8_t)~(uint8_t)0x01U;                          

  /* MCG_C10: LOCRE2=0,??=0,RANGE1=2,HGO1=1,EREFS1=1,??=0,??=0 */

  MCG_C10 = (uint8_t)0x2CU;                            

  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=1 */

  MCG_C2 = (uint8_t)0x21U;                            

  /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

  MCG_C1 = (uint8_t)0xA8U;                            

  /* MCG_C4: DMX32=0,DRST_DRS=0 */

  MCG_C4 &= (uint8_t)~(uint8_t)0xE0U;                          

  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */

  MCG_C5 = (uint8_t)0x04U;                            

  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */

  MCG_C6 = (uint8_t)0x08U;                            

  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=4 */

  MCG_C11 = (uint8_t)0x04U;                            

  /* MCG_C11: PLLCLKEN1=1 */

  MCG_C11 |= (uint8_t)0x40U;           /* Enable the PLL */

  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=8 */

  MCG_C12 = (uint8_t)0x08U;                            

  while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */

  }

  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */

  }

  /* Switch to PBE Mode */

  /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */

  MCG_C6 = (uint8_t)0x48U;                            

  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */

  }

  while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked */

  }

  /* Switch to PEE Mode */

  /* MCG_C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

  MCG_C1 = (uint8_t)0x28U;                            

  while((MCG_S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */

  }

  /* MCG_C6: CME0=1 */

  MCG_C6 |= (uint8_t)0x20U;            /* Enable the clock monitor */

  /*** End of PE initialization code after reset ***/

#endif

7.- Go to line 315 in init_hw.c which is located in C:\Freescale\Freescale MQX 3.8\mqx\source\bsp\twrk70f120m. You must comment the line that calls DDR2 initialization.

/* Initialize SDRAM */

//    _bsp_ddr2_setup();

8.- Now you must rebuild TWR-K70 BSP. This porject is located in C:\Freescale\Freescale MQX 3.8\mqx\build\cw10\bsp_twrk70f120m. You only need to drag and drop .project file into CW workbench and rebuild this project.

9.- Clean and build the application. In this case it is 'K70_MQX_DDR2_Target' project. Notice that a folder with the name of the new Build Configuration (K70_EXT_DDR2) is created.

10.- Create 'Debugger' folder inside the 'Projects_settings' folder. Copy MK70FN1M0.mem and init_twr_k70_ddr2.tcl files in this folder.

NOTE: The debugger will use *.tcl to communicate with the MCU. We take advantage of this file to configures DDR2 also. MK70FN1M0.mem will tell the debugger where to find DDR2 memory address.

11.- Select menu Run > Debug Configurations... Right click on Internal RAM debug configuration and select New.

12.- In the Application box select the .afx file created inside the folder of the Build Configuration you created. In this case it is K70_EXT_DDR2.

13.- Create a new connection for K70 using MK70FN1M0.mem and init_twr_k70_ddr2.tcl init files.

14.- Click Debug. Now you are debugging from DDR2.

Hope this helps!

CAMC

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seandema
Contributor IV

Any chance there is an example of doing this with newer versions of CW and MQX? I'm trying to do this in CW 10.6 and MQX 4.2 built using the GCC tool chain and am having some troubles.

I'm using the .tcl and .mem files from the attachment above. However I may have messed something up in going from .lcf to the .ld used for GCC compiled projects.

See my other post about this.

Debug K70 on external RAM with MQX & CW 10.6 GCC

Thanks,

Sean

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Carlos_Musich
NXP Employee
NXP Employee

Hi Sean,

we are working on your question in the other thread

Regards,

Carlos.

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Carlos_Musich
NXP Employee
NXP Employee

Hi Todd,

The task you want to perform is not easy with MQX. You can find below the steps I followed do it.

1.- Create a new MQX3.8.1 project in CW10.2 using the New Project wizard and select it in the CodeWarrior projects workbench. I will call this project 'K70_MQX_DDR2_Target'.

NOTE: Make sure that your connection type is OSBDM. This project is not tested with J-link.

2.- Click menu Project > build Configurations > Manage

3.- Click New. In the window prompted name your new Build Configuration K70_EXT_DDR2 and select Copy Sttings from Existing Configuration. Select Internal RAM, click OK and click OK again.

NOTE: Make sure that the active Build Configuration is the one that was just created. Check this in menu > Project > Build Configurations > Set active

4.- Create 'Linker_Files' folder inside Projects_Settings Folder and copy K70_DDR2.lcf contained in this attachment.

5.- Click menu Project > Properties > C/C++ Build > Settings > ColdFire Linker > Input and browse for K70_DDR2.lcf. Click OK.

NOTE: Some edits must be done to the BSP. The reason is that the clock and the DDR2 module are configured by the debugger using init_twr_k70_ddr2.tcl. But MQX has its own clock and DDR2 configuration. If MQX overwrites these configurations the debug session will fail. So we need to avoid that MQX initializes the PLL and the DDR2.

6.- Go to line 995 in bsp_cm.c. This file is located in C:\Freescale\Freescale MQX 3.8\mqx\source\bsp\twrk70f120m. Below you can find the code snippet that must be disabled. To disable the code I put it between #if 0... #endif directives.

#if 0

/* MCG_C7: OSCSEL=0 */

  MCG_C7 &= (uint8_t)~(uint8_t)0x01U;                          

  /* MCG_C10: LOCRE2=0,??=0,RANGE1=2,HGO1=1,EREFS1=1,??=0,??=0 */

  MCG_C10 = (uint8_t)0x2CU;                            

  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=1 */

  MCG_C2 = (uint8_t)0x21U;                            

  /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

  MCG_C1 = (uint8_t)0xA8U;                            

  /* MCG_C4: DMX32=0,DRST_DRS=0 */

  MCG_C4 &= (uint8_t)~(uint8_t)0xE0U;                          

  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */

  MCG_C5 = (uint8_t)0x04U;                            

  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */

  MCG_C6 = (uint8_t)0x08U;                            

  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=4 */

  MCG_C11 = (uint8_t)0x04U;                            

  /* MCG_C11: PLLCLKEN1=1 */

  MCG_C11 |= (uint8_t)0x40U;           /* Enable the PLL */

  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=8 */

  MCG_C12 = (uint8_t)0x08U;                            

  while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */

  }

  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */

  }

  /* Switch to PBE Mode */

  /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */

  MCG_C6 = (uint8_t)0x48U;                            

  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */

  }

  while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked */

  }

  /* Switch to PEE Mode */

  /* MCG_C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

  MCG_C1 = (uint8_t)0x28U;                            

  while((MCG_S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */

  }

  /* MCG_C6: CME0=1 */

  MCG_C6 |= (uint8_t)0x20U;            /* Enable the clock monitor */

  /*** End of PE initialization code after reset ***/

#endif

7.- Go to line 315 in init_hw.c which is located in C:\Freescale\Freescale MQX 3.8\mqx\source\bsp\twrk70f120m. You must comment the line that calls DDR2 initialization.

/* Initialize SDRAM */

//    _bsp_ddr2_setup();

8.- Now you must rebuild TWR-K70 BSP. This porject is located in C:\Freescale\Freescale MQX 3.8\mqx\build\cw10\bsp_twrk70f120m. You only need to drag and drop .project file into CW workbench and rebuild this project.

9.- Clean and build the application. In this case it is 'K70_MQX_DDR2_Target' project. Notice that a folder with the name of the new Build Configuration (K70_EXT_DDR2) is created.

10.- Create 'Debugger' folder inside the 'Projects_settings' folder. Copy MK70FN1M0.mem and init_twr_k70_ddr2.tcl files in this folder.

NOTE: The debugger will use *.tcl to communicate with the MCU. We take advantage of this file to configures DDR2 also. MK70FN1M0.mem will tell the debugger where to find DDR2 memory address.

11.- Select menu Run > Debug Configurations... Right click on Internal RAM debug configuration and select New.

12.- In the Application box select the .afx file created inside the folder of the Build Configuration you created. In this case it is K70_EXT_DDR2.

13.- Create a new connection for K70 using MK70FN1M0.mem and init_twr_k70_ddr2.tcl init files.

14.- Click Debug. Now you are debugging from DDR2.

Hope this helps!

CAMC

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adishieber
NXP Employee
NXP Employee

I wanted to know if there is a more recent example for this on later versions of CW and MQX running from DDR.

Thanks,
Adi

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Carlos_Musich
NXP Employee
NXP Employee

Here is the attachment.

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stephenchorlton
Contributor II

I am also trying to run an MQX project from DDR, but I am using the GCC compiler and C++.

Using your notes and by changing the .ld file I have put the code into DDR, but the code will only run if I single step to the start of MQX.

If I let the code free run from the start it jumps back to trying to run in the Flash memory. Once I have MQX setup and I let the code free run it works OK.

I think it is something to do with the interrupt vector setup.

Have you any suggestions?

Thanks,

Steve

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