I'm using TWR-K70 and TWR-SER.
I'm initialize port first..
and then
MK70_SIM_REGISTER_SCGC2 |= MK70_SIM_SCGC2_ENET1_MASK; // Clock On
HardwareEthernet.SystemEndian = memory_get_system_endian();
hardware_ethernet_reset(); // Reset
hardware_ethernet_disable(); // Disable Block
MK70_ENET_REGISTER_EIMR = 0; // Mask all FEC interrupts
MK70_ENET_REGISTER_EIR = 0xFFFFFFFF; // Clear all FEC interrupt events
// MK70_ENET_REGISTER_EIR = MK70_ENET_EIR_TS_TIMER_MASK
// | MK70_ENET_EIR_TS_AVAIL_MASK
// | MK70_ENET_EIR_WAKEUP_MASK
// | MK70_ENET_EIR_PLR_MASK
// | MK70_ENET_EIR_UN_MASK
// | MK70_ENET_EIR_RL_MASK
// | MK70_ENET_EIR_LC_MASK
// | MK70_ENET_EIR_EBERR_MASK
// | MK70_ENET_EIR_MII_MASK
// | MK70_ENET_EIR_RXB_MASK
// | MK70_ENET_EIR_RXF_MASK
// | MK70_ENET_EIR_TXB_MASK
// | MK70_ENET_EIR_TXF_MASK
// | MK70_ENET_EIR_GRA_MASK
// | MK70_ENET_EIR_BABT_MASK
// | MK70_ENET_EIR_BABR_MASK;
// Clear MAC address
MK70_ENET_REGISTER_PALR = 0;
MK70_ENET_REGISTER_PAUR = 0;
// Clear the Individual Address Hash registers
MK70_ENET_REGISTER_IALR = 0; // Set unicast address hash table
MK70_ENET_REGISTER_IAUR = 0; // Set unicast address hash table
// Clear the Group Address Hash registers
MK70_ENET_REGISTER_GALR = 0; // Set multicast address hash table
MK70_ENET_REGISTER_GAUR = 0; // Set multicast address hash table
// Set interrupt mask
// Enable Transmit Frame Interrupt, Receive Frame Interrupt, BUS Error Interrupt
// MK70_ENET_REGISTER_EIMR = (MK70_ENET_EIMR_TXF_MASK | MK70_ENET_EIMR_RXF_MASK | MK70_ENET_EIMR_EBERR_MASK);
MK70_ENET_REGISTER_EIMR = 0
| MK70_ENET_EIMR_BABR_MASK
// | MK70_ENET_EIMR_BABT_MASK
// | MK70_ENET_EIMR_GRA_MASK
| MK70_ENET_EIMR_TXF_MASK
// | MK70_ENET_EIMR_TXB_MASK
| MK70_ENET_EIMR_RXF_MASK
| MK70_ENET_EIMR_RXB_MASK
// | MK70_ENET_EIMR_MII_MASK
| MK70_ENET_EIMR_EBERR_MASK
// | MK70_ENET_EIMR_LC_MASK
// | MK70_ENET_EIMR_RL_MASK
// | MK70_ENET_EIMR_UN_MASK
| MK70_ENET_EIMR_PLR_MASK
// | MK70_ENET_EIMR_WAKEUP_MASK
// | MK70_ENET_EIMR_TS_AVAIL_MASK
// | MK70_ENET_EIMR_TS_TIMER_MASK
;
// Set PAUSE frame duration
MK70_ENET_REGISTER_OPD = (MK70_ENET_OPD_OPCODE(0x00) | MK70_ENET_OPD_PAUSE_DUR(0x00));
// Set transmit control register
MK70_ENET_REGISTER_TCR = (MK70_ENET_TCR_ADDSEL(0x00) | MK70_ENET_TCR_FDEN_MASK); // Enable Full Duplex
// Set transmit accelerator function configuration register
MK70_ENET_REGISTER_TACC = 0x00000000; // disable insert protocol checksum, IP header checksum, and TX fifo shift
// Set receive control register
MK70_ENET_REGISTER_RCR = MK70_ENET_RCR_MII_MODE_MASK /*always*/
| MK70_ENET_RCR_RMII_MODE_MASK /*We using RMII mode*/
| MK70_ENET_RCR_MAX_FL(ETHERNET_FRAME_MAXIMUM_LENGTH) /*check frame length*/
| MK70_ENET_RCR_FCE_MASK; /*Flow control enable*/
// | MK70_ENET_RCR_CRCFWD_MASK; /*no CRC pad required*/
// Set receive accelerator function configuration register
MK70_ENET_REGISTER_RACC = 0x00000000; // not discard Error frame, wrong checksum frame and IP header checksum error frame, pad not removed, and RX fifo shift
// Set transmit inter-packet gap
MK70_ENET_REGISTER_TIPG = MK70_ENET_TIPG_IPG(0x08/*8~27*/);
// Set frame truncation length
MK70_ENET_REGISTER_FTRL = MK70_ENET_FTRL_TRUNC_FL((((ETHERNET_FRAME_MAXIMUM_LENGTH/*1518*/ % 64) != 0) ? (((ETHERNET_FRAME_MAXIMUM_LENGTH/*1518*/ / 64) + 1) * 64) : ETHERNET_FRAME_MAXIMUM_LENGTH));
// Set transmit FIFO watermark
MK70_ENET_REGISTER_TFWR = (MK70_ENET_TFWR_STRFWD_MASK | MK70_ENET_TFWR_TFWR(0x00)); // Store & forward enable transmit FOFO write 64 bytes written
// Set transmit FIFO section empty threshold
MK70_ENET_REGISTER_TSEM = MK70_ENET_TSEM_TX_SECTION_EMPTY(0x00);
// Set transmit FIFO almost empty threshold
MK70_ENET_REGISTER_TAEM = MK70_ENET_TAEM_TX_ALMOST_EMPTY(0x08);
// Set transmit FIFO almost full threshold
MK70_ENET_REGISTER_TAFL = MK70_ENET_TAFL_TX_ALMOST_FULL(0x08);
// Set receive FIFO section full threshold
MK70_ENET_REGISTER_RSFL = MK70_ENET_RSFL_RX_SECTION_FULL(0x00);
// Set receive FIFO section empty threshold
MK70_ENET_REGISTER_RSEM = MK70_ENET_RSEM_RX_SECTION_EMPTY(0x00);
// Set receive FIFO almost empty threshold
MK70_ENET_REGISTER_RAEM = MK70_ENET_RAEM_RX_ALMOST_EMPTY(0x08);
// Set receive FIFO almost full threshold
MK70_ENET_REGISTER_RAFL = MK70_ENET_RAFL_RX_ALMOST_FULL(0x08);
// Set MII speed control register
hardware_ethernet_mii_initialize();
// Clear statistic counters
hardware_ethernet_clear_statistics();
// Set default MAC address
hardware_ethernet_set_mac_address(HardwareEthernet.pMAC);
// Buffer Initialize
hardware_ethernet_buffer_initialize();
hardware_interrupt_set_prority(INTERRUPT_NUMBER_ENET_TRANSMIT, INTERRUPT_PRIORITY_6);
hardware_interrupt_set_prority(INTERRUPT_NUMBER_ENET_RECEIVE, INTERRUPT_PRIORITY_6);
hardware_interrupt_set_prority(INTERRUPT_NUMBER_ENET_ERROR, INTERRUPT_PRIORITY_6);
hardware_ethernet_phy_initialize();
hardware_ethernet_enable();
hardware_interrupt_enable(INTERRUPT_NUMBER_ENET_TRANSMIT);
hardware_interrupt_enable(INTERRUPT_NUMBER_ENET_RECEIVE);
hardware_interrupt_enable(INTERRUPT_NUMBER_ENET_ERROR);
then... not occur interrupt.
when polling 'MK70_ENET_REGISTER_EIR'
TX frame interrupt bit is set when transmit
TX frame interrupt bit is set when receive
but not occur interrupt.
any one help me?
Hi
Have interrupts been enabled in the Cortex core, as well as in the EMAC?
Regards
Mark
followings are display a enabling core interrupt
hardware_interrupt_enable(INTERRUPT_NUMBER_ENET_TRANSMIT);
hardware_interrupt_enable(INTERRUPT_NUMBER_ENET_RECEIVE);
hardware_interrupt_enable(INTERRUPT_NUMBER_ENET_ERROR);
........................
int hardware_interrupt_enable(qInterruptNumber InterruptNumber)
{
return core_nvic_interrupt_enable((uint32_t)InterruptNumber);
}
int core_nvic_interrupt_enable(uint32_t InterruptNumber)
{
if(InterruptNumber < 240)
{
if((CORTEX_M4_PERIPHERAL_REGISTER_NVIC_ISER(InterruptNumber >> 5) & (1 << (InterruptNumber & 0x0000001F))) == 0)
{
CORTEX_M4_PERIPHERAL_REGISTER_NVIC_ICER(InterruptNumber >> 5) |= (1 << (InterruptNumber & 0x0000001F));
CORTEX_M4_PERIPHERAL_REGISTER_NVIC_ISER(InterruptNumber >> 5) |= (1 << (InterruptNumber & 0x0000001F));
return 0;
}
return 2;
}
return 1;
}
#define CORTEX_M4_PERIPHERAL_REGISTER_NVIC_ISER(Index) (CORTEX_M4_PERIPHERALS_POINTER->NVIC_ISER[Index])
#define CORTEX_M4_PERIPHERAL_REGISTER_NVIC_ICER(Index) (CORTEX_M4_PERIPHERALS_POINTER->NVIC_ICER[Index])
Hi Stephanos,
is it necessary for you to use the Ethernet module in a bareboard project? Have you thought on using a stack? This is most common as it provides many services. May I ask what is your application? We provide RTCS (Real Time Communications Suite) in MQX, this stack provides TCP/IP support and many other protocols, this could be useful for you. You can take a look in www.freescale.com/mqx
Best regards,
Carlos