Hardware floating point on TWR-K60F120M

[aimozg]

When I was trying to benchmark FPU on TWR-K60F120M, I got some problems when trying to run even simplest application with floating-point instruction.

I've started modifying KINETIS_120MHZ_SC example, added some simple float code. It run without problems with software floating point, but when I switched to hardware, I've got an exception. (Hard Fault with No Coprocessor Usage Fault).

It was strange since according to all documentation PK60FN1M0VLQ12 has single-precision FPU. After studying ARM documentation, I've found the problem: the coprocessors should be explicitly enabled.

I didn't find related register constant in CPU header file, so I've added them (file attached, modified register info from line 14940 to 15311). So adding the following code enables FPU (and it is about ten or more times faster than software emulation):

// Enable CP10 and CP11
SCB_CPACR |= SCB_CPACR_CP10_MASK | SCB_CPACR_CP11_MASK;

[J2MEJediMaster]

Yes, that is a known issue with the CW compiler, in that it does not explicitly enable the FPU when you use single-precision floating-point arithmetic. The other gotcha is that you must declare all constants with an F suffix so that they are treated as single-precision values. Otherwise, per the C standard, the compiler treats them as double-precision and generates calls to the software floating-point libraries.

Hope this helps,

---Tom