Glitch filter setting of the IRQ-pin of KEA

[hiroyoshi_suzuk]

Hi

I have a basic questions about the IRQ-pin function of KEA128. So, please help me.

Q1 : Glitch filter setting for the IRQ-pin
According to the KEA128 reference manual rev2, there are the following setting bits.
   PORT_IOFLT0[FLTRST]  :  for RESET-pin and IRQ-pin ( Section 6.2.2.1.1 also explain this. )
   PORT_IOFLT1[FLTIRQ]   :  for only IRQ-pin

Are these correct? Or, is the FLTRST-bit a mistake of only for a RESET-pin?

Q2 : KEA128 has both PORT_IOFLT0 and PORT_IOFLT1. But KEA64 has only one register of PORT_IOFLT.

Can't user use glitch filters for peripheral such as PWT or FTM if user is using KEA64?

Thank you very much in advance.

BR,

Hiroyoshi

[jingpan]

Hi,

1. IRQ function can be assigned to several pins. I think this means when you assign IRQ to PTA5, you should use PORT_IOFLT0[FLTRST] to set filter. You can make a experiment to verify it. Setting PTA5 as IRQ function and enable the filter by FLTRST. Another pin send a short pluse to trig IRQ. If no IRQ happen, it means FLTRST can control this pin.

2. Yes, it seems KEA64 PWT and PWM input can use filter.

Regards,

Jing

[hiroyoshi_suzuk]

Hi Jing-san

Thank you for your replay.

I think this means when you assign IRQ to PTA5, you should use PORT_IOFLT0[FLTRST] to set filter.

My understanding is, the glitch filter is located at each port pins, not at each internal module.

Because, Figure 11-1 to Figure 11-3 shows that the glitch filter is located at each port pins.

And, section 11.4 also said as “A filter is implemented for each port pin that is configured as a digital input.”

However, is my understanding wrong? And each glitch filter is located at internal module like a KBI or IRQ or etc.? And doesn’t it influence changing the pin assignment by SIM module?

BR,

Hiroyoshi

[jingpan]

Hi,

Yes, you are right. As you can see, the filter is in IO circuit. But KEA and KE family is a bit special. The pins control signal is gathered in function group. It seems the filter control signal is also take by group.

Regards,

Jing

[hiroyoshi_suzuk]

Hi Jing-san

Thank you for your help. Maybe, I understood about the glitch filter structure of KEA. But, let me confirm my understanding.

The following my understanding is correct?

1, KEA has two kind of Glitch filter. One is for GPIO and other is for internal functions such as NMI or KBI or etc.

2, The glitch filter in the Figure 11-1 to Figure 11-3 shows only for GPIO.

3, User needs to enable the glitch filter for function which user is using. (Either GPIO or internal function.)

For example, if user use the PTB4/NMI –pin as GPIO, user needs to enable FLTB(glitch filter for PTB).

But if user use this pin as NMI, user needs to enable FLTNMI (glitch filter for NMI).

FLTB setting and FLTNMI setting is separated and doesn’t influence each other.

In this case, FLTB setting doesn’t influence to FLTNMI.

4, If user use the PTA5/RESET/IRQ-pin as a RESET-pin or an IRQ-pin, user needs to use FLTRST for glitch filter setting.

But, if user assigned the IRQ function to other than PTA5, and then if user wants to use glitch filter for IRQ, user needs to enable FLTIRQ.

FLTRST setting and FLTIRQ setting also doesn’t influence each other.

Please let me know if I misunderstood something.

And, the following is my image for glitch filter structure of KEA.

By the way, page 156 of RM shows as the below. The FLTE-bit assignment is for a PTE instead of a PTD, correct?

BR,

Hiroyoshi

[jingpan]

Hi,

I made a demo to test the filter function. When PTA5 pin is configured from RESET to IRQ, FTLRST can still control this pin. So, the RM is right. If I try to use FLTA, it couldn't work.

I don't think there are two kind of filter. There is only one kind of digital filter in the I/O pin. This digital filter controlled by different control bit in different signal multiplexing.

Yes, this is a typo. It should be PTE. Thanks.

Regards,

Jing