FRDM-KL46Z Internal Reference clock to 48 MHz?

[ishmeets]

I am working on IAR compiler for FRDM-KL46Z Platform.

I want to use Internal clock and set it to 48 MHz (or as maximum as possible).

Till now I have done the following steps in the example sysinit.c file and function sysinit() provided.

#define NO_PLL_INIT

#if defined(NO_PLL_INIT)

mcg_clk_hz = 48000000;     // It only works on 21000000 Hz, otherwise I get garbage prints on UART0.

SIM_SOPT2 &= ~SIM_SOPT_PLLFLLSEL_MASK

uart0_clk_khz = (mcg_clk_hz) / 1000;

#else

....

In FEI mode, if I do FBI mode or BLPI mode, I get very less mcu clock.

I want the mcu clk to be as high as possible, in internal clock. (According to datasheet I think it is supported, but I don't know how?)

Can anyone please explain or any code reference, much obliged.

[ishmeets]

Fixed it by doing this

#define NO_PLL_INIT  
#if defined(NO_PLL_INIT)  
MCG_C4 |= (MCG_C4_DRST_DRS(1) | MCG_C4_DMX32_MASK); 
mcg_clk_hz = 48000000;  
SIM_SOPT2 &= ~SIM_SOPT_PLLFLLSEL_MASK; 
uart0_clk_khz = (mcg_clk_hz) / 1000;  
#else ....

[galadragos]

UART0 has selective clock source!

See SIM->SOPT2[UART0SRC] .