DMA and SPI

[MikeR]

Any examples of using a DMA channel with the SPI?   

 I want to modify a driver I have that interfaces to an external NOR flash part to use DMA to write and read the data.   Currently, the driver code just brute force loops through the data to write or read

and consumes the processor while doing so.

How do you set up the DMA to fill the TXFIFO in the SPI, and also DMA out of the RXFIFO queue?

What goes into the TXFIFO queue?   It normally holds both SPI command and data.  So, do you have to append that command data to the buffer of data to DMA and then let it DMA it?

What kind of loop do you set up for the DMA?   The Fifo queues are only four enties long, but I'll probably want to

read/write 1024 bytes each time, as this interfaces to a flash file system.

Will I need to copy the data to a static buffer, ro can I point the DMA to a buffer the caller provides?

[riccardo_catto]

Has everyone configured a SPI + DMA full duplex transfer port?
Is possible to have an example code to start from?

Thanks

[PeterFromSweden]

I am also struggling with DMA and SPI.

I guess that just connecting SPI to DMA request doesn't let you transfer more than one SPI-character a time, since the DMA request must trigger every character (like interrupts). This means innerloop bytecount 1 and outerloop iteration count as the desired number of characters.

I cannot find any app example that shows this. Any hints?

[BryGuyH]

The simple answer is don't bother. The DSPI is frankly the worst dma connected SPI module in the industry and will not work the way you want it to (as a master that is), you will never get the throughput you would expect. But if you want to use it...the biggest things you have to make sure of is:

a) configure DMA transfer size for 32 bits (1 word) for both ends of the transfer. (this is because the eDMA module is going to do nothing more than copy data in your array right into the PUSHR for the spi channel you are interested in. As soon as you write to the PUSHR register it gets loaded into the TX fifo)

b) Make sure arrays are aligned.

c) preprocess the array you want to transfer from a byte array into a word array: Make sure to load the spi commands into the upper two bytes for each element in the word array

d) you should be able to use any memory as long as its aligned... however if you try to reference memory off the stack I wouldn't trust that you wouldn't get a bus fault, in that regard its probably best to make sure its either an allocated block from a memory manager, or static buffer.

So you have two choices... use 4x the memory for each transfer and sacifice the cycles to preprocess your arrays on tx and postprocess on rx... or simply run in polled or interupt driven modes. In the case of nand flash with a page size of 2112 bytes that means 8448 of ram per DMA transfer direction.

[lisa_tx]

Hi BryGuyH,

        I am looking a way to configure DMA transfer for SPI on K60 too. Do you mean that this SPI DMA transfers one 32-bit word a time? Among this 32-bit word, upper half is command. It actually transfers 16-bit real data a time? If this is the case, why does K60 bother to offer a DMA method? We can use interrupt service routine to handle each word data transfer, don't we? What is the difference between interrupt transfer and DMA transfer in this case? 

        Thanks!

Lisa