DMA Circular Buffer transfers

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DMA Circular Buffer transfers

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stevecolley65
Contributor I

Hi Everyone, I am using a KL25Z on the FRDM-KL25Z board. My question is about using the DMA circular buffer mode. The only DMA interrupt option I see is an interrupt request at the end of a transfer. However, in circular mode, it is not practical to do anything with the data in the buffer, in response to the interrupt, if another transfer is starting right away. The data in the beginning of the buffer will be quickly overwritten by the next transfer. Is there a way to get an interrupt request at another place in the transfer? For example, at 50%? What am I missing?

There must be a relationship between the buffer size and the transfer size which I don't understand. Does someone have more info on this or an example?

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mjbcswitzerland
Specialist V

Hi

The simplified DMA controller, as used in most KL parts, can only generate an end of transfer interrupt.

However it can perform endless transfers if set up in modulo mode (the circular buffer length needs to be a multiple of 2 and the buffer aligned on a memory alignment that is in divisible by the buffer size).

Interrupts are not available in this mode but as long as the buffer is large enough the transfer progress can be polled at a relaxed rate in order to prepare or remove data before the buffer is reused/overwritten.

Other Kinetis K parts and some of the newer KL and KE ones support full featured DMA controllers so are a better choice if there are specific requirements for DMA/interrupt features.

Regards

Mark
[uTasker project developer for Kinetis and i.MX RT]
Contact me by personal message or on the uTasker web site to discuss professional training, solutions to problems or rapid product development requirements

For professionals searching for faster, problem-free Kinetis and i.MX RT 10xx developments the uTasker project holds the key: https://www.utasker.com/kinetis/FRDM-KL25Z.html

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stevecolley65
Contributor I

Thank you! Good to know. Perhaps a better approach anyway is to link two channels back and forth to form dual buffer memories. Then, an ISR can refresh the "just finished" DMA channel and coordinate the buffer switching with processing tasks. I will look into this setup. The reference manual does not say much about linking channels. Hopefully two channels can share the same DMA Request source.

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