Continuous Overwrite of C(n)V register with FTM Input Capture

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Continuous Overwrite of C(n)V register with FTM Input Capture

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aberger
Contributor V

I would like to continuously capture both rising and falling edges on two separate pins using dual edge capture on an FTM module on a K64. Is it possible to set up the capture registers C(n)V to be continuously overwritten, even if I am not reading the register and clearing the CH(n)F bit with each new edge?

I can't afford to service each edge as it comes in, so my goal is to fire an ISR on the FTM overflow, and then read the input captured time of the most recently-received edge, which could be on any of the four registers (corresponding to rising or falling edges on each of my two pins). From Fig. 40-83 in the K64 Reference Manual, it is not clear whether I need to clear the CH(n)F and CH(n+1)F registers in order to capture the next edge.

Fig_40-83.png

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470件の閲覧回数
aberger
Contributor V

I figured this out:

  • if you never clear the CH(n)F bit, the C(n)V register will be constantly updated to the latest value (see e.g. the sequence of events from (7) - (10) in the above figure).
  • if you do clear the CH(n)F bit after a rising edge but before a falling edge, you can prevent the next pair of events from being captured (see e.g. the sequence of events from (11) - (14) above). However, clearing the CH(n+1)F bit after a rising edge but before a falling edge does not have the same effect, since it will simply be re-set on the next falling edge, causing both the most recent rising edge and falling edge to be captured to the C(n)V and C(n+1)V registers, respectively.

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471件の閲覧回数
aberger
Contributor V

I figured this out:

  • if you never clear the CH(n)F bit, the C(n)V register will be constantly updated to the latest value (see e.g. the sequence of events from (7) - (10) in the above figure).
  • if you do clear the CH(n)F bit after a rising edge but before a falling edge, you can prevent the next pair of events from being captured (see e.g. the sequence of events from (11) - (14) above). However, clearing the CH(n+1)F bit after a rising edge but before a falling edge does not have the same effect, since it will simply be re-set on the next falling edge, causing both the most recent rising edge and falling edge to be captured to the C(n)V and C(n+1)V registers, respectively.
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