instruction cache problem wiht MCF5475

[salocin68]

Hello,

I encounter some problems when enabling the instruction cache on my MCF5475 custom board.

The system hangs up just after writing in the CACR/ACR register... if the instruction cache is disabled, all is perfect.

The MCF54x5 simple project is used for this test.

On a Zoom devboard, I can not reproduce this phenomen. The only difference between my custom board and the Zoom one, is the memory which is a SDRAM and not a DDRAM...

Any idea ?

Thanks in advance

Nicolas

[J_rg]

Be sure to clear all cache content before enabling it (bits DCINVA, BCINVA and ICINVA in the CACR).

Regards,
Jörg

[JWW]

Nicolas,

Have you made any progress on this issue? If I had to take a guess, it's not a cache problem, but probably a SDRAM controller configuraton problem.

Typically, I would look at two things if I saw this sort of problem. Check how you are progamming the burst length of the SDRAM and the actual controller. Also, make sure you are routing the SDR_DQS signal from the 547x/8x part to the DQS inputs on the 547x/8x. This signal allows the DDR controller to connect to SDR memories.


-JWW

[salocin]

Hi JWW,

I'm always fighting against my cache problem. I found something strange which explains why the cache does not work with my SDRAM.

I checked the SDRAM burst length (8) and the timings as well. All is ok and works perfectly wihtout the cache.

I have to 16bits SDRAM which form a 32bits data bus.

Here is the sequence causing my troubles:

The cache is enabled (write through) and I perform a read/write access (32bits, value 0x01020304) to the first SDRAM address (0x00000000). The readback value is ok.

Now I write an other value (0x05060708) to the second 32bits address (0x00000004). If i read back the value, I get 0x01020304 ???? 

Do you have an idea ?

Thanks in advance

Best regards,

Nicolas 

[salocin]

Hi JWW,

Problem is now resolved. The LMR register of the SDRAM was not correctly programmed (wrong define).

Thanks for the tips.

Best Regards

Nicolas

[salocin]

Hi,

Sorry for the delay to your last post.

The DQS line is correctly routed and I'm able to read and write to the SDRAMs without any problems if the caches (instruction/ data) are disabled. So I assume that the physical interface is ok.

Now I have read something strange in the MCF547x Ref Manual Rev 3.

In the figure 18-6 it is written that the Burst length (A2-A0) must be one in case of SDR...and must be 8 if a MCF547x is used.

Now I have a 5475 controller with SDRAM attached. What should I do ????

Thanks in advance

Best Regards,

Nicolas