how MCF52232/MCF52236 replace MCF52233/52235?

[gxd]

I used MCF52233 and mcf52235 CPU for 2 years before.

MCF52233 system clock is 60MHz but new product is 50MHz.

For new product MCF52232/MCF52236 ,how to revise old source code in this change?

(the source code is based  on AN3455 ).

void
mcf5223_pll_init(void)
{
 /* The PLL pre-divider affects this!!!     no change!
  * Multiply 25Mhz reference crystal /CCHR by 12 to acheive system clock of 60Mhz
  */

 MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(4) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;

 while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
 {
 }
}

ADD:

MCF_CLOCK_CCHR=0x05;            ////            25MHz*12/6=50MHz

Whether need I do more thing except there?

Message Edited by gxd on 2008-10-13 08:25 AM

[gxd]

I try it but the ethernet not pass.

i redefine SYSTEM_CLOCK  50 (mcf52235evb.h)

I find the problem in there:

void mcf5223_ePHY_init(void)
{
 uint32   myctr;      //generic counter variable
 uint16   mymrdata, mymwdata;     //temp variable for MII read/write data
   uint16  reg0, reg1, reg4;    //

 fec_mii_init((SYSTEM_CLOCK));

......

}

Need more ?

[mjbcswitzerland]

Hi

MCF_CLOCK_CCHR can not be changed - see the errata (this may however be corrected in newer chips).

For 60MHz operation MCF_CLOCK_SYNCR is set to 0x4007 ((25MHz / 5) * 12).
For 50MHz operation MCF_CLOCK_SYNCR is set to 0x3007 ((25MHz / 5) * 10).

Regards

Mark

www.uTasker.com



Message Edited by mjbcswitzerland on 2008-10-14 11:08 AM

[MrBean]

mjbcswitzerland wrote:

MCF_CLOCK_CCHR can not be changed - see the errata (this may however be corrected in newer chips).

In newer chips it indeed can be changed, very limited though.

See:

http://forums.freescale.com/freescale/board/message?board.id=CFCOMM&message.id=2316&jump=true