That gave me a bit of trouble when I was checking the SDRAM programming on our MCF5329 based product too.
The ISSI data sheet defines DESELECT as any cycle with /CS driven high, and NOP as any cycle where /CS is low, but /RAS, /CAS and /WE are all high. With both of these /CKE has to be high on the previous cycle.
CKE is asserted by setting the CKE bit in the SDCR register. This is a normal part of initialisation. Your first write to SDCR will set the CKE bit.
The SDRAM clock is running all the time. That means that every clock cycle between "real commands" is a DESELECT command or a NOP.
Have a look at the ISSI data sheet Read and Write cycle timing diagrams. The "commands" are listed like "READ NOP NOP NOP READ NOP NOP NOP ..."
> How do I do this using the SDRAMC?
Just delay in the initialisation code. While the CPU is doing nothing the SDRAM controller will be generating 80 million NOPs or DESLs per second.
After you've finished the "official" SDRAM initialisation I'd recommend you perform a few dummy burst reads and burst writes. Either use MOVEM.L assembly instructions or enable the data cache (with write-through) and perform some read and write cycles. If I didn't do that I found that the first burst read from the SDRAM (reading instructions after copying code from FLASH to SDRAM) returned corrupted data. Others have had this happen to them too. The bursting might not be necessary, and normal reads might work find, but I fixed this problem with bursts and haven't bothered to see what other combinations might work instead.
Tom
