MCF547x Interrupt latency

[salocin]

Hello,

In my current project, I need to relatively react quickly to an external interrupt.

After some measurements, I found that the processor needs more than 700ns after the interrupt edge to enter in the interrupt routine !!!

I have no operating system, the interrupt code/data are located in the core RAM and this interrupt has the highest priority level.

The system bus freq is 100MHz while the core frequency is 200MHz.

Any ideas ????

Nicolas

[Rik]

Hello.

I've been fighting a MCF5485 for months.

There seems to be a major problem with the core to XLB bus connection. Maybe that's the source of your problem too. I did a test for reading memory (move.l) , the code was in core SRAM1 and this was what I got:

reading core SRAM0, 1 cycle

reading sys SRAM, 20 cycles !!!

The answer I got was that there are 2 "gaskets" which the core has to pass to the XLB.

Cheers,

RIk.

ps. Also the DMA task swapping is enormously slow.

[salocin]

Hi Rik,

Thanks for the informations. I'm in the same situation as you.... Fighting against this buggy chip.

I will no more used a V4 core for my next designs. The chip specifications were quite good on the paper but the real behaviour is far from what was announced

What's the benefits of a 200MHz core frequency if the rest of the chip is running 10 to 20 times slower ???

Good luck...

Nicolas