Pascal,
The secret with SDRAM, DDR, DDR2 is to make sure each data byte lane is matched up with its control signal.
The bit significance within a byte lane does not matter, and can be routed to match the efficiencies of your layout. Of course it is always better to pick some sequential manner. The biggest mistake you could make is to route data lines across control boundaries. In DDR and DDR2 you have DM (data masks) and DQS (data strobes). And they are assigned in both the processor and the memory to specific data lines.
Example:
DQ[31:24] normally is DQS[3]
DQ[23:16] would be DQS[2]
ETC. ETC...
The memories will often refer to the DQS signals as UDQS or LDQS. For upper byte or lower byte...strobes.
Also, you asked about the /LDQS signals. In DDR2 you can use differential DQS signals. The 5445x family does not need differential DQS, as 133Mhz clock does not really justify the extra signals. This is typically used on systems that need 200Mhz clock and 400Mhz data or faster. So these signals are not used on the SDRAMs. If you look at the data sheet for a DDR2 RAM, you'll see that there is a LOAD MODE register command that you have to run to enable the inverted DQS outputs from the RAM.
If you haven't already read the application note we have, it may be a good idea. And we are always open to feedback if you would like to see more info in the current application note or if you need another version that answers different questions.
Lastly.. DDR and DDR2 are not that hard to do.
Weblink:
http://www.freescale.com/files/32bit/doc/app_note/AN3522.pdf?fpsp=1&WT_TYPE=Application%20Notes&WT_V...-JWW