This chip has a very simple watchdog. The Reference Manual makes it clear how to use it.
Just write a byte to CWCR to enable the watchdog to reset the CPU after an appropriate timeout (between 2^9 and 2^31 bus clocks), and then regularly write the required values to CWSR from some appropriate execution path in your code.
When the Watchdog triggers you'll lose all ability to find out what went wrong. I usually set up a hardware watchdog and also a software one (spare timer casuing an NMI) set to trip before the hardware one does that prints where it interrupted the mainline and that the hardware watchdog is about to trigger.
The fact that the last reset was caused by the watchdog is available in the RSR. You should check this on startup and do something sensible (like count it in EEPROM) if the last reset was caused by the watchdog.
Tom
