Memory exception when writing to Quicc Engine User PRAM

[shermie]

Hi

Hopefully I am posting this to the correct area.

I am modifying a single core network driver to one that will service all cores for the MSC8156 (running on a MSC8156EVM).  This driver is used on another OS (i.e. not SmartDSP)

I have setup the registers on the quicc engine to allow for 6 Tx and Rx queues (i.e. one per core).  The receive side appears to be working as expected however I have a slight issue with the Tx side.

I place the data into the buffer and set the BD up and then when I come to increment the CPU counter in the scheduler I get an exception (0x158 - DMMUAE).

The M_DVA register indicates that it is the correct location within the Multi User RAM of the Quicc Engine (0xFEE1BD20) but the M_DSR specifies

"A data access does not match an enabled data segment descriptor"

The line of code and the asemmbler is below

1410	(*(driver_info->tx_packet_CPU_Counter))++;

c0002760:   move.w #$38,r2

c0002762:   move.l (sp-$24),r3

c0002764:   adda r3,r2

c0002766:   move.l r2,(sp-$20)

c0002768:   move.l (sp-$20),r4

c000276a:   move.l (r4),d0

c000276c:   move.l d0,(sp-$20)

c000276e:   [ move.l (sp-$20),r1   syncio  ]

c0002774:   [ moveu.w (r1),d1   syncio  ] <-- Exception

I have even tried setting it to a value rather than an increment but still get the same result.

I believe I have set the registers up as they should.  For example if I was to stop the code using the JTAG at the point I should increment the counter and increment it manually using the debugger watch window (or memory window) then the packet is sent out as expected.

I have tried a few experiments to see when I can write to the MURAM and when I can't.  It seems to be in the following order

Write to MURAM causes an exception before a reset command is sent to QE

Write to MURAM is ok (i.e. while I set up all the Eth Structures)

Write to MURAM causes an exception after the Init ENET command

Any help would be appreciated as I have drawn a blank.

Thanks in advance

Paul

Original Attachment has been moved to: exceptionafterincrement.regs.zip

[shermie · Accepted solution]

Managed to solve the issue.  Just incase someone else hits a similar problem and finds this question the answer is below.

The reason is that during certain operations on the QUICC Engine memory the MPE bit in the MMU Control Register needs to be cleared to ensure an exception isn't raised when modifying memory.  This bit should be set again once finished.