I am using CW ver 5.0 for S12X and am developping for a S12XEQ384.
I my linker PRM file, I have:
PAGE_FD_CALS = READ_ONLY 0x7F7000'G TO 0x7F7FFF'G RELOCATE_TO 0x0FD000'G;
In my map file, I see the expected RAM address for a variable in this segment:
P_PCtl_DiffKdMax FDD3F'G
However, the debugger tells me the address is FD1D3F, neither a valid logical address nor global address
Solved! Go to Solution.
FDD3F'G is the global address corresponding to FD1D3F'L.
What do I miss?
Daniel
FDD3F'G is the global address corresponding to FD1D3F'L.
What do I miss?
Daniel
Oops. Sorry. All the banking stuff can get confusing.