error: LS1020A: Core not responding while bringing up custom board .

[dhruvalkumarpat]

Hi All I have custom board with LS1020A . I am trying to bring it up for the first time . I am using code warrier tap (USB) . I got following error (logged in code warrier server )

check_min_version(serverh=0,*version)

  api version: 00000004 00000006

get_connection_count(serverh=0,cc_index=0,*count)

  count:1

available_connections(serverh=0,*count,*cc)

  connections: {0,73,0xa9fe0d39}

available_connections(serverh=0,*count,*cc)

  connections: {0,73,0xa9fe0d39}

available_connections(serverh=0,*count,*cc)

  connections: {0,73,0xa9fe0d39}

available_connections(serverh=0,*count,*cc)

  connections: {0,73,0xa9fe0d39}

available_connections(serverh=0,*count,*cc)

  connections: {0,73,0xa9fe0d39}

available_connections(serverh=0,*count,*cc)

  connections: {0,73,0xa9fe0d39}

cc_version(serverh=0,cc_index=0,index=0,*version)

get_config_chain(serverh=0,cc=0)

config_server(config_reg=0,config_data=0x00002710)

config_chain(serverh=0,cc=0,count=3,*devlist,*generic)

  devlist: ls1020a,dap,sap2

write_register(coreh.{serverh=0,cc_index=0,chain_pos=0},index=0,size=4,*reg)

  reg: 0000009E

config_template(coreh.{serverh=0,cc_index=0,chain_pos=0},config_reg=4096,config_data=0x00000001)

write_register(coreh.{serverh=0,cc_index=0,chain_pos=0},index=4102,size=4,*reg)

  reg: 40025A00

write_register(coreh.{serverh=0,cc_index=0,chain_pos=0},index=4103,size=4,*reg)

  reg: 21046000

write_register(coreh.{serverh=0,cc_index=0,chain_pos=0},index=4104,size=4,*reg)

  reg: 00000000

write_register(coreh.{serverh=0,cc_index=0,chain_pos=0},index=4105,size=4,*reg)

  reg: 00000000

write_register(coreh.{serverh=0,cc_index=0,chain_pos=0},index=4106,size=4,*reg)

  reg: 00000000

write_register(coreh.{serverh=0,cc_index=0,chain_pos=0},index=4107,size=4,*reg)

  reg: 00038000

write_register(coreh.{serverh=0,cc_index=0,chain_pos=0},index=4108,size=4,*reg)

  reg: 20024800

write_register(coreh.{serverh=0,cc_index=0,chain_pos=0},index=4109,size=4,*reg)

  reg: 24049340

write_register(coreh.{serverh=0,cc_index=0,chain_pos=0},index=4110,size=4,*reg)

  reg: 00000000

write_register(coreh.{serverh=0,cc_index=0,chain_pos=0},index=4111,size=4,*reg)

  reg: 00000000

reset_to_debug(serverh=0,cc=0)

  ERROR(39): Subcore error encountered during multicore operation

parse_error_ext(coreh.{serverh=0,cc_index=0,chain_pos=0}, 39)

  error: LS1020A: Core not responding

reset_to_debug(serverh=0,cc=0)

  ERROR(39): Subcore error encountered during multicore operation

parse_error_ext(coreh.{serverh=0,cc_index=0,chain_pos=0}, 39)

  error: LS1020A: Core not responding

reset_to_debug(serverh=0,cc=0)

  ERROR(39): Subcore error encountered during multicore operation

parse_error_ext(coreh.{serverh=0,cc_index=0,chain_pos=0}, 39)

  error: LS1020A: Core not responding

Dose any one have any idea about it. I tried to use hard coded RCW option . Am I missing any jtag chain config ??

[kbell_hardware]

I am having this same problem on a T2080 custom board, was there ever a fix found for this?

[yipingwang]

Hello Dhruvalkumar Patel,

Please check whether there is hardware problem on your custom target board.

Please download "AN4878, QorIQ LS1021A Design Checklist - Application Note" from QorIQ LS1021A Dual-Core Communications Processor wi|NXP , and refer to "Figure 31. JTAG interface connection" to check your JTAG interface design, especially nRESET pin.

Have a great day,
Yiping

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[addiyi]

Please take a look on chapter Hard-coded RCW options from LS1021 RM, and choose the value for rcw_src according with your board configuration. One of hard-coded option should work for your board and "Core not responding" error in ccs should gone.

Adrian

[dhruvalkumarpat]

It seem the SYSCLK  default source IFC_WE0_B is  1 means its not selecting DIFF_SYSCLK which is the default clock source in our case.

[addiyi]

Please try using in ccs console, followings commands and provide the output.

config cc cwtap

ccs::config_chain { ls1020a dap sap2 }

ccs::config_template 0 0x1000 1

ccs::write_reg 0 rcw_src 0x9A 

ccs::reset_to_debug

Adrian

[dhruvalkumarpat]

Thanks for suggestion .

I tried this before and now and I received following messages

(bin) 1 % config cc cwtap

(bin) 2 % ccs::config_chain { ls1020a dap sap2 }

(bin) 3 % ccs::config_template 0 0x1000 1

(bin) 4 % ccs::write_reg 0 rcw_src 0x9A

(bin) 5 % ccs::reset_to_debug

LS1020A: Core not responding

(bin) 6 %

[addiyi]

What is the value for SYSCLK and DDRCLK for your board?

Adrian

[dhruvalkumarpat]

Source  is 100 MHz

CPU clock  = 800 Mhz

DDR clock  = 600 Mhz

[dhruvalkumarpat]

I tried to scan the jtag chain and I get following result.

bin) 19 % source IDcode.tcl

Scanning for available TAPs connected via USB.....

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

+

+      Available Remote Connections

+

+   1 -  CodeWarriorTAP  -  00:04:9f:03:b1:4c

+   2 -  CodeWarriorTAP  -  <Specify IP Address>

+   3 -  GigabitTAP  -  <Specify IP Address>

+

+   x  - Exit Script without Changes

+

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Specify connection:

1

Configuring TAP Interface....

Configured Connection: cwtap : 00:04:9f:03:b1:4c

TDO -----

        |

        * Device 0  IDCODE: 5BA00477  Device: Unknown Device

        * Device 1  IDCODE: 16B0001D  Device: FSL LS1 Device rev 2.x

        |

TDI -----

###################################################

#

#    configTAP -  Redefine TAP interface

#

#    scanboard -  Scans the target system

#    and returns the JTAG IDCode                

#

#    ir  -  Loopback test

#

###################################################

But error still persist