Hi
In our latest codewarriro QCVS, the margin page of DDR validation doesn't have Margin stage as scenarios, only has Diags margin stage. Why this happen? What's the cause?
Thanks.
Margin stage is removed since QCVS 4.23 2020.11 release.
Margin stage scenario is no longer available for LX2, but is should be available for the rest of devices.
If further information is needed, please feel free to let me know.
Please open CCS console on the right bottom of your task bar, type "log v", then connect to the target board again, the low level CCS log will be printed out.
Please send the CCS console log to me to do more investigation.
Would you please refer to "3.2 Working with bareboard application" in the attached document to create a board board project and run it on your target board.
Please click "Target Connections->LX2160A_RDB(1)->Edit->Target Initialization File",
please modify "USE_SAFE_RCW = False" to "USE_SAFE_RCW = True".
Then connect to the target board, and send CCS console log to me, I just want to check whether the core can be stopped.
Please also try the following commands in CCS console.
delete all
config cc cwtap:<ip>
ccs::config_chain {lx2160a dap}
display ::ccs::get_config_chain
::ccs::stop_multi_core {21}
::ccs::reset_to_debug