Timer in QL4

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

Timer in QL4

2,406 次查看
DVD_Boost
Contributor I
I need to make an application which has a free running counter or a PWM to generate a signal with square form and duty cycle 50%. This signal will have variable ratio, changed dynamically in the code. Except this I need also an interrupt each 10ms for handling some other events.
How can I combine these two counters in QL4?
标签 (1)
0 项奖励
8 回复数

546 次查看
peg
Senior Contributor IV
Hi DVD_Boost,
 
I am a bit confused, one minute you say 50% PWM then you say variable ratio. Its not PWM unless you "modulate" it.
What Frequency PWM do you require, perhaps you can fudge this so that 10ms is a multiple of the PWM period and place a counter inside the ISR?
 
0 项奖励

546 次查看
DVD_Boost
Contributor I
Sorry peg, my fault.
I ment variable period. More detailed this is a sound with 50% constant ratio.How can I generate the sound and still have a timer tick event 10ms (or less, but constantly) to handle other functionality of the application (example LIN message handling).
 
I'm sorry, this project was a half year aside but the question is still hot for me.
0 项奖励

546 次查看
peg
Senior Contributor IV
Hi again,
 
Then you probably need to set to toggle on compare and have a compare interrrupt that calculates the next toggle point and loads that up.
Presumably the 10ms signal is the timer overflow?
 
0 项奖励

546 次查看
DVD_Boost
Contributor I
I was afraid that I need to do that.
But this means that I will have a huge amount of interrupts when a sound is generated (leterally each tougling of the sound signal). Is this secure in case I do not want to miss any LIN message- I know I have a SLIC hardware controller which is holding the last ID and data of the message but may be there is a chanse that I miss a message anyway...? 
0 项奖励

546 次查看
bigmac
Specialist III
Hello,
 
The ISR code to set the next output compare value need not be very complex - my estimate is a total of 43 cycles to complete.  This assumes that the default TMOD value is not changed.  Assuming use of a 6.4MHz bus frequency, this would then require 6.7 microseconds for the ISR processing.  A 6.4MHz bus frequency would also give a timer overflow period of nominally 10.24 milliseconds, very close to what you need.
 
The minimum allowable audio frequency would be 50 Hz, and the maximum I suspect would need to be kept below about 2000 Hz (with an interrupt occurring every 250 us, or 1600 cycles).
 
I am not familiar with LIN to know what are the critical timing issues related to the handling of a message.  However, I might suspect there would be more possibility of the LIN message processing, within an associated ISR, causing disruption to the tone output.
 
For the estimate given above, the following ISR code was assumed for TIM channel 0.  The estimate also included 9 cycles required tor entry to the ISR.
 
  BCLR CH0F,TSC0    ; CLEAR FLAG
  LDX  TCH0H
  LDA  TCH0L
  ADD  PERIODVAL    ; LS BYTE OF TONE HALF PERIOD
  PSHA
  TXA
  ADC  PERIODVAL+1  ; MS BYTE OF TONE HALF PERIOD
  STA  TCH0H
  PULA
  STA  TCH0L
  RTI
 
Regards,
Mac
0 项奖励

546 次查看
DVD_Boost
Contributor I
Thank you Mac,
 
Now I have some idea how to proceed further.
 
Regarding the sound, I need the highest frequency a bit higher so the interrupts will occure even faster.
I think I just have to live with the fact that the sound will be disturbed from the LIN processing. The quality of it is not that important anyway.
 
Best regards.
Pavel
0 项奖励

546 次查看
peg
Senior Contributor IV
Hi Pavel,
Not sure about your exact device but normally the timer interrupt is a higher priority than the SCI and if they were to get in each others way you may have to take extra care that it will be the sound being affected by the LIN and not the other way around.
 
0 项奖励

546 次查看
DVD_Boost
Contributor I
Good advice Peg,
 
I'm going to check the datasheet regarding the priority of the timer against LIN.
Thank you.
 
Best regards.
Pavel
0 项奖励