Hello Andrea,
You do not say which device you are using. However, I will assume a HCS08 device, and that you are controlling the transmission direction using the SCIC3_TXDIR control bit.
There are two possibilities. The first one is that the SCIC2_TE bit remains continuously active, and with the following sequence of events required to complete a transmission.
- Set TXDIR bit to 1 for send operation.
- Write first send character to SCID register.
- If further characters to be sent, wait until TDRE flag bit is set before writing each subsequent character.
- After final send character is written, wait until TC flag bit becomes set.
- Set TXDIR bit to 0 for further receive operation.
The first send character should commence immediately after the first character is written to SCID.
The second possibility is that the TE control bit is set to 1 immediately preceeding step 1 above, and is then cleared to 0 following step 5. This will cause an additional idle character to be sent prior to the first send character, thus delaying the commencement of the first send character by the byte transmission period.
Regards,
Mac
Message Edited by bigmac on
2008-08-28 11:31 PMMessage Edited by NLFSJ on
2008-08-30 10:28 AM