SPI slave driver for S08DZ60

[italiandoh]

Hello, I need to setup a SPI driver in slave mode for a S08DZ60 in order to communicate with another processor (which will be master of SPI communication). Is there anything available that could be used or adapted for this purpose ? I've searched the forum and also looked into Freescale site but I couldn't find anything useful. Please help if you can. Any suggestion is welcome Thanks and best regards, Matteo

[pbouf]

I'm currently implementing an SPI Slave but with a different MCU (QE64/QE128). Here are some considerations to look in to:

- The SPI clock speed, which is controlled by the master. If it's too fast, the MCU won't be able to keep up and you will loose some data.

- The master expecting the slave to return a byte at a specific offset. This works good on deterministic ASIC or FPGA devices like serial PROMs but if the MCU has tasks other than just waiting for the SPI interrupt to occur, chances are you won't be able to always provide the data when the master expects it.

In order to have a perfect master and the slave communication, I had to introduce a framing concept based on Async-HDLC (RFC1662) where the slave had lots of time to prepare a transmit buffer and the master just had to send some dummy bytes (FLAG IDLE bytes to be more precise) every once and a while to retrieve the data from the slave. No timing issue.

Good luck!

[italiandoh]

Hello, thank you to everyone for your inputs and suggestions. Best regards, Matteo

[peg]

Hello Mateo,

Driver?

Usually you would simply set the SPI up to match the master then read the data register whenever it becomes full.

[PeterHouse]

Don't forget to load the Tx Register with the data to transfer on the next send from the Master. This data will be transferred when the Master clocks the data to the slave. After you receive the next data sent from the Master you should put the next byte in the Tc register as soon as possible after reading the Rx data since you do not know when the Master will transfer the next byte. Depending on the Master, this could happen very very quick! Good Luck, Peter House

[bigmac]

Hello,

A slave SPI application will usually involve the use of interrupt on SPI receive, so that it is possible for other work to be done by the MCU whilst waiting for SPI events.  If the data to be returned is determined by the byte value just received, there will be some delay until the first return byte can be written to the SPI data register, ready for interrogation by the SPI master.  The master must therefore allow a suitable worst case delay before attempting to interrogate the returned data.  This delay should additionally allow for the execution of any other interrupt sources.

If the worst case delay is potentially large, but may vary over a wide range, it may be more efficient to provide "handshaking" back to the master, using a GP output pin, to indicate when the return data is ready.  This is in addition to the SS signal originating from the master.

When multiple bytes are to be returned by the slave, keep in mind that this is an instance where the double buffering associated with SPI send may prove very useful to minimize the delay required once the data stream has started.

Regards,

Mac