MC9S08AC60 SPI (Slave) - can SS be permanently tied low (active) with CPHA=1?

[mfugere]

I have a design with (2) MC9S08AC60 microcontrollers, (1) SPI Master and (1) SPI slave.   On the slave, I am configuring the SPIC1 bits = SPIE | SPE | CPHA | SSOE and  SPIC2 bits = 0x00 as I need the SPI to run/wake the slave from WAIT instructions.   The SS line on the slave is tied to GND with 10K resistor instead of the Master's SS output pin (which I could change)  I seem to have inconsistent SPI interrupts on the slave, is it necessary for the SS to toggle high-low at all for slave's interrupts to work properly, or can it remain permanently tied low?  I know with CPHA = 0, SS must go high in between successive byte transmissions.  The previous design's chip MC908GP32 had its SS tied low and appeared to work consistently.  The MC9S08AC datasheet indicates the SS must go low at the start of data transmissions, and can remain low for successive bytes, but it doesn't indicate taht the SS could be left active/low all the time.

[mfugere]

Yes, I tend to agree that SS needs to be a controlled signal from the master.   There are other oddities about the original design which I think I'll be changing, such as gating the SPI Clock between a DAC and the slave CPU instead of gating SS signals to enable/disable each slave..

[scottm]

I'd be worried about the potential for framing errors to creep in if SS is always low.  I would assume that SS being de-asserted resets the shift register on the slave.  Without any synchronization mechanism it seems like a single SPSCK glitch would throw it out of whack.  Even if you can get the interrupts you need out of it, I don't think I'd try.

Scott