Hello Gary,
To avoid stack usage, I assume the RAM test would need to be inline, within your main loop, and the execution paced by means of a timer overflow interrupt, or something similar, that would set a flag bit to initiate each test. You might also consider using unused (and benign) peripheral read/write registers for temporary storage purposes, and for keeping track of the next address to be tested. For example, unused TPM channel registers might be suitable contenders.
I am not sure about the "coupling faults" issue. This would seem to imply that every other RAM address would need to be tested for change, as the test address value was changed. Since storage is very limited, this would appear feasible only a single byte at a time, for each test value at the test address, making each test very time consuming.
Regards,
Mac