Hi Roger,
The order you have shown is the unstacking order, the stacking order is opposite!
Stacking operations are normally last in, first out.
Quote from GP manual:
"An interrupt does not stop the operation of the instruction being executed, but begins when the current instruction completes its operation"
So there you go, concern unfounded!
BR Peg
Hi,
I don't think you are correct here, says me, mouthing of before I check for sure.
Peg
"When an interrupt occurs, The CCR value is saved on the stack before the I bit is automatically set (I would be 0 in the stacked CCR value). When the return-from-interrupt (RTI) instruction is executed to return to the main program, the act of restoring the CCR value from the stack normally clears the I bit.
When the I bit is set, the change takes effect too late in the instruction to prevent an interrupt at the instruction boundary immediately following an SEI or TAP instruction. In the case of setting I with a TAP or SEI instruction, I is actually set at the instruction boundary at the end of the TAP or SEI instruction. In the case of clearing I with a TAP or CLI instruction, I is actually cleared at the instruction boundary at the end of the TAP or SEI instruction. Because of this, the next instruction, after a CLI or TAP that cleared I, will always execute even if an interrupt was already waiting when the CLI or TAP that cleared I was executed. In the case of the RTI instruction, the CCR is restored during the first cycle of the instruction so the 1-cycle delay, associated with clearing I, expires several cycles before the RTI instruction finishes. WAIT and STOP also clear I in the middle of the instruction, so the delay expires before actually entering wait or stop mode.
"
My bad... I'm sure there a way to get blocked though.
Even a bigger cheque for you then !?
Alvin. {RTFM}
The restoring of the registers is done in a single instruction (RTI), and because the interrupt status is examined by the CPU at the completion of (not in the middle of) each instruction, all the registered will be restored before entering the next ISR.
Sten
Just don't forget to pshh and pulh if you change/use it. That register isn't automatically saved, and if you happen to use it...