Bad break char sent by SCI on AP32

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Bad break char sent by SCI on AP32

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StefanoQ
Contributor I
Hi all,

I'm facing the following problem.
I use SCI on AP32 for a packet communication on RS485.
Cpu clock is produced by the PLL with an external 32kHz crystal.
Bus clock is 7372800Hz.
Baud rate is 38400 (26us/bit)
The start of packet is marked by a break character.
When I start the transmisison of a packet I do the following
1) enable tx driver and disable rx receiver on RS485 driver.
2) disable reception on SCI SCC2 = 0x08 (TE bit is always setted)
3) trigger break transmission: SCC2 = 0x09 (TE=1, SBK = 1) then SCC2 = 0x48 (TE = 1, SBK = 0, TCIE = 1)

What I see is that the break character on TxD pin stay low level for 247us instead of 260us (Start+8bit+stop, a half bit period missed) and the receiver doesn't recognize the break so it does not start packet parsing. On the following packet bytes the duration of bits is correct (26us).
Furthermore, the other unit on the RS485 bus transmits similar packets in the opposite direction using the the same uC (AP32) but using IRSCI module and with the same register config sequence, in this case producing a well timed break character on TxD pin.

Do anyone see something wrong in what I do or do you know different procedure to send a break char?

Thanks a lot.

Bye,
    Stefano


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erooll
Contributor II
Hi..
Maybe you are disabling Tx on 485 before all break byte was transmited?
probe setting a delay before do it (disable TX).
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StefanoQ
Contributor I
Dear erool,

actually I've seen the problem directly on the TxD pin of the uC.
Nevertheless, the Tx enable line is deactivated only at the end of the packet, that is, 4 bytes later.

Thanks,
Stefano
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bigmac
Specialist III
Hello Stefano,
 
What you seem to be saying is that when the two SCI modules are setup identically, one SCI module produces a break timing error of one half bit period, whereas the other one produces the correct timing.  Have you checked for any Mask Set Errata documents?
 
If you happen to have discovered an (at least publicly) undocumented bug, perhaps your only recourse may be to hold the SBK bit active for greater than one break period so that the duration of the break signal is extended by an additional period.
 
Regards,
Mac
 
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