Why when I slow down the internal clock on the QE4 does the BDM step time take FOREVER, its impossilby slow.
i.e. clock setting
ICSC1 = 0b01000110; //Slow internal clock For normal operation
ICSC2 = 0;
Dear CalrIFST60L,
The internal clock is at around 35 kHz. You would expect the BDM interface to be really sloooow if you change the bus clock to such a low value. By default the BDM interface runs at the Bus clock (/2?).
Two possibilities
- You didn't actually mean to bypass the FLL by changing the CLKS bits in the ICSC1. If not, check your values (see 11.3.1 of the manual).
- Configure your BDM so that it sets the CLKSW bit in the BDCSCR register so that the BDM uses the alternative BDM clock (ICSLCLK ~ 8MHz).
bye