what is the difference between S12X and S12z MagnaV core?

[ameykhatavkar]

I need to find quick difference S12X and S12Z MAgnaV core. I am going through the online available stuff, but it is on immediate basis.

Is the things implemented on S12x core are directly portable on MagnaV core?

If not, I would like to know the what are the blockage or things to take care.

[RadekS]

Hi Amey,

Unfortunately there isn’t any direct migration guide between S12X and S12Z.

In fact, S12X and S12Z cores are built on different platform architecture (S12Z use Harvard architecture with parallel data and code access).

However many CPU features, instructions and principles are (almost) the same.

The main advantage of S12Z core is linear address space (no more pages and calculating between global and local addresses). It uses a 24-bit address bus, Stack Pointer, Program Counter and Index registers.

S12Z Data Bus Width is 32-Bit RAM & Flash, 16-Bit I/O. ALU Width is 32-bit. Data Registers are 2 x 8-Bit, 4 x 16-Bit, 2 x 32-Bit. Pointers are 2 x 24-Bit. Re-defined op-code set improves code size efficiency and performance. Fractional Math Support – Fixed Point.

S12Z has only one System Reset Vector (0xFFFFFC). Reset and Interrupt vectors have 4 bytes (for store 3 byte address). Optimized for smaller context saving (10 bytes on S12Z vs. 29 bytes on S12X).

For more details please look at

http://www.nxp.com/files/microcontrollers/doc/ref_manual/S12ZCPU_RM_V1.pdf

http://www.nxp.com/files/microcontrollers/doc/ref_manual/S12XCPUV2.pdf

and few attached slides.

Many peripherals for S12Z are the same or similar to S12X peripherals, however some of them are significantly different. For example: ADC.

I hope it helps you.

Have a great day,
RadekS

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[ameykhatavkar]

Hi Radek,

Thanks for the replay. Its really very helpful.Thanks for the mentioning in details.

Radek, are currently working on MC9S12xDP512  and wanted to port the things on MC9Z12ZVM128.

Is there any difference with the timer module and interrupts vector in both??

Where I got the more details about the Interrupt handling?

``

Regards,

Amey

[RadekS]

Hi Amey,

There are just few changes between ECT module in S12XD and TIM module in S12Z in basic principles.

TIM module is simplified version of ECT module (missing pulse counter and modulus down counter features).

Additionally OCPD register in TIM module is responsible for disconnecting between Output Compare channel and Pin.

Other basic principles are the same.

Vector tables are different (S12X have 16bit vectors, S12Z have 32bit vectors) and order of interrupts are different. Please check Table 1-16. Interrupt Vector Locations in RM.

Vector number for S12Z could be calculated as (0x1FC-Vector Address)/4.

Interrupt handling is described in CPU reference manuals:

http://www.nxp.com/files/microcontrollers/doc/ref_manual/S12ZCPU_RM_V1.pdf

http://www.nxp.com/files/microcontrollers/doc/ref_manual/S12XCPUV2.pdf

I hope it helps you.

Have a great day,
RadekS

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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