Enabling MMU and Caches on i.MX6 Series Platform SDK

[#1]

Installation, patching and building the SDK

The i.MX 6 Series Platform SDK v1.1.0 does not enable neither the MMU nor L1/L2 Caches (depending on the benchmark you are running, enabling these yield much better numbers), so there is a need to patch the code to enable these. Please download the SDK from the Freescale portal and the patch attached on this document, then follow these instructions:

$ tar zxvf imx6_platform_sdk_v1.1.0.tgz

$ cd iMX6_Platform_SDK

$ patch -p1 < 0001-add-L2-cache-enable-to-mx6-SDK-1.1.0.patch

$ export PATH=$PATH:<toolchain_install_path>/bin

$ ./tools/build_sdk

For more help, please look at the README.pdf and documents inside the doc folder.

[synthnassizer]

Hello there, I am abit fuzzy about the usage of platform_SDK.

I am using a iMX6 Sabre-Lite board. will I be needing this SDK?

What sort of options does it offer. Mind you I did look into the sources before asking here, but I am abit lost.

Thank you for your help.

[LeonardoSandova]

Hi Nass, please download the tarball and check the README.pdf. I believe you get the info you need.

[EdSutter]

Has Ethernet been tested with dCache enabled?

[i386]

Hello,

About the SDK v1.1, I am always puzzled about the interrupt vector table. In the link script file(.lds), the interrupt vector table locates at the bottom of OCRAM. And in mmu_init(), the OCRAM is mapped to the same address as physical. So the interrupt vector base will not be 0x00000000. How do the arm core fetch it's interrupt vector when an interrupt occur?

[LeonardoSandova]

Mike, could you please post your the above on a new discussion thread?