Example S32K144 RAM Retention S32DS.R1

Document created by Diana Batrlova Employee on Jan 22, 2019Last modified by Diana Batrlova Employee on Jul 26, 2019
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Detailed Description:

This example shows the use of SRAM retention after SW reset.
The SW reset is triggered by pressing the SW3 button on the S32K144 EVB

The reset is delayed in RCM module: 514 LPO cycles.

In the RCM interrupt, SRAMU_RETEN and SRAML_RETEN are cleared allowing to retain SRAM data during the reset.

After software reset, SRAMU_RETEN and SRAML_RETEN are set to1 to allow accesses to SRAM. 

During software initialization in the startup_S32K144.S, ECC RAM initialization is skipped. 

After that, we can check the written data before reset are still placed in the SRAM.
Test HW: S32K144EVB-Q100
MCU: S32K 0N57U
Debugger: S32DSR1