i.MX6UL PWM output clock not stable issue

Document created by Shaojun Wang Employee on Mar 26, 2017Last modified by Adrian Puga Candelario on Jan 21, 2020
Version 4Show Document
  • View in full screen mode

On L4.1.15 BSP, PWM output clock may be not stable, for example, it may switch between 200KHz and 50KHz.

PWM clock source is perclk, in running mode, perclk is 24MHz, while in low power idle mode, perclk is reduced to 6MHz, so PWM output clock is reduced to 1/4.

To keep PWM output stable clock, we should let perclk stay in 24MHz in low power idle mode.

Attached is the patch for 6UL and 6ULL.